Patent application number | Description | Published |
20080310061 | Transistor with EOS protection and ESD protection circuit including the same - A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape. | 12-18-2008 |
20090080129 | Semiconductor chips having improved electrostatic discharge protection circuit arrangement - A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads. | 03-26-2009 |
20100208400 | Pad interface circuit and method of improving reliability of the pad interface circuit - The pad interface circuit includes a first stack MOS transistor having a first terminal connected to a pad and a bulk connected to a first supply voltage; a second stack MOS transistor having a first terminal connected to a second terminal of the first stack MOS transistor and a second terminal, a gate terminal, and a bulk that are connected to the first supply voltage; and a voltage level sensing circuit generating a feedback voltage by using a pad voltage applied from the pad. In addition, the feedback voltage is applied to a gate terminal of the first stack MOS transistor. | 08-19-2010 |
20100214705 | Electrostatic discharge protection element and electrostatic discharge protection circuit including the same - An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode. | 08-26-2010 |
20110199346 | SEMICONDUCTOR DEVICE HAVING GUARD RING, DISPLAY DRIVER CIRCUIT, AND DISPLAY APPARATUS - A semiconductor device includes a semiconductor substrate having a first conductivity type, at least two first well regions which have a second conductivity type and a predetermined depth in the semiconductor substrate, at least one second well region which has the first conductivity type and a predetermined depth in each of the first well regions, and a guard-ring region which has the second conductivity type and a predetermined depth and is positioned between the first well regions to be separated by a predetermined distance from the first well regions. The guard-ring region is connected to a ground voltage. | 08-18-2011 |
20130182359 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit includes a first power line; a second power line; a ground line; two stack transistors connected in series between the first power line and the ground line; a first resistor connected between the first power line and a first node; a first transistor and a capacitor connected in series between the first node and the ground line; a second transistor connected between the second power line and a second node; a third transistor connected between the first power line and a third node; an inverter, connected between the third node and the ground line, and having an input connected to the second node; a fourth transistor, connected to the first power line, and having a gate connected to the second node; and a fifth transistor, connected between the second power line and the third node, and having a gate connected to a terminal of the fourth transistor. | 07-18-2013 |
20140306296 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer. | 10-16-2014 |
20140316760 | METHOD OF THREE-DIMENSIONAL OPTOELECTRICAL SIMULATION OF IMAGE SENSOR - A three-dimensional optoelectrical simulation includes generating a process simulation result including a doping profile of a silicon substrate of image sensor, a structure simulation result with respect to a back end of line structure, and a merged result generated by merging a process simulation result and a structure simulation result, selectively extending the merged result to an extended result by using a process simulation result or a structure simulation result, generating a segmented result for each pixel based on a merged result or an extended result, an optical crosstalk simulation result of image sensor based on a structure simulation result and an optical mesh, and a final simulation result including an electrical crosstalk simulation result of the image sensor based on a segmented result for each pixel and an optical crosstalk simulation result. | 10-23-2014 |
20140332883 | Semiconductor Device Having Dummy Gate and Gate - A fin-shaped active region is defined on a substrate. First and second gate electrodes crossing the fin-shaped active region are arranged. A dummy gate electrode is formed between the first and second gate electrodes. A first drain region is formed between the first gate electrode and the dummy gate electrode. A second drain region is formed between the dummy gate electrode and the second gate electrode. A source region facing the second drain region is formed. A first drain plug relatively close to the dummy gate electrode, relatively far from the second gate electrode, and connected to the second drain region is formed. The second gate electrode is arranged between the second drain region and the source region. Each of the first and second gate electrodes covers a side surface of the fin-shaped active region. | 11-13-2014 |