Patent application number | Description | Published |
20080285596 | SYSTEM AND METHOD FOR FINE-GRAINED, END-TO-END TRAFFIC SCHEDULING ACROSS HETEROGENEOUS LOCAL AREA NETWORKS - A system and method for fine-grained, end-to-end traffic scheduling across heterogeneous local area networks (LANs). A system may include a network, where the network comprises multiple heterogeneous network, technologies. The system also may include at least two devices coupled to the network, where clocks of the at least two devices are synchronized. The system also may include a scheduler coupled to the network, where the scheduler creates a network wide data traffic schedule and where the data traffic schedule determines when each of the at least two devices can send data into the network. Other embodiments are described and claimed. | 11-20-2008 |
20090077141 | Aggregation of file/directory structures - In general, in one aspect, the disclosure describes a method that includes maintaining a superset of data available to a client having non volatile memory (NVM) on a distant hard drive. A subset of the data is maintained in the NVM on the client. The client controls the data maintained on the distant hard drive and the data maintained in the NVM. A single merged directory/file structure is generated from a directory/file structure of the superset and a directory/file structure of the subset. The directory/file structures overlap and the single merged directory/file structure merges the overlapping directory/file structures so only the directory/file structure of the subset is presented for the overlap. The single merged directory/file structure is presented to a user of the client and applications running thereon. | 03-19-2009 |
20090168935 | METHODS AND APPARATUS FOR SYNCHRONIZING NETWORKED AUDIO DEVICES - A method includes determining a network counter value indicative of a network clock time of a system at a first time instant and a second time instant occurring later in time than the first time instant. The method further includes determining an audio counter value indicative of an audio clock time of the system at a third time instant occurring the first and second time instants and a fourth time instant occurring later in time than the second time instant. The method further includes determining an offset based upon the determined network counter values and the audio counter values. The method further includes adjusting the audio clock time based upon the determined offset to synchronize operation of at least one audio component operating according to the audio clock with at least one audio component operating according to the network clock. An associated system is also disclosed. | 07-02-2009 |
20090241179 | Enabling peripheral communication in a local area network - In one embodiment, the present invention includes a component to be coupled to a peripheral device to enable the peripheral device to appear to be locally connected to a computer of a local area network, although the peripheral device is not physically connected to the computer. The component may include a first set of registers to store a mirrored copy of control register information present in a second set of registers of a host controller interface of the computer. Other embodiments are described and claimed. | 09-24-2009 |
20090327683 | SYSTEM AND METHOD TO ACCELERATE ACCESS TO NETWORK DATA USING A NETWORKING UNIT ACCESSIBLE NON-VOLATILE STORAGE - In some embodiments, the invention involves a network controller having a pattern matching unit to identify whether boot file requested from a network accessible storage device for booting are stored locally in non-volatile memory accessible to the network controller. When required boot files are stored locally, the locally stored files are sent to the processor to boot the operating system. In an embodiment, retrieved boot files are automatically cached by the network controller in the accessible non-volatile memory. In other embodiments, a service operates to ensure coherency between locally store boot files and the boot filed stored on the network accessible storage. In another embodiment, data other than boot files may be stored and retrieved from the non-volatile memory. Other embodiments are described and claimed. | 12-31-2009 |
20100174830 | SYNCHRONIZING MULTIPLE SYSTEM CLOCKS - Techniques are disclosed for synchronizing multiple clock sources of a system, and may include: determining time of a first clock at a first and second time instants; determining time of a second clock at a third time instant occurring between the first and second time instants, and a fourth time instant occurring after the second time instant; and determining a clock offset between the first and second clocks based on the determined times. The first and/or second clocks may be adjusted based on the clock offset to synchronize clock operation. This adjusting can be used, for instance, to synchronize operation of an audio and/or video component operating according to the first clock with an audio and/or video component operating according to the second clock. The techniques may further include determining if the clock offset is valid (e.g., based on detection of perturbing events or difference between a clock's times). | 07-08-2010 |
20120170597 | SYNCHRONIZING MULTIPLE SYSTEM CLOCKS - Techniques are disclosed for synchronizing multiple clock sources of a system, and may include: determining time of a first clock at a first and second time instants; determining time of a second clock at a third time instant occurring between the first and second time instants, and a fourth time instant occurring after the second time instant; and determining a clock offset between the first and second clocks based on the determined times. The first and/or second clocks may be adjusted based on the clock offset to synchronize clock operation. This adjusting can be used, for instance, to synchronize operation of an audio and/or video component operating according to the first clock with an audio and/or video component operating according to the second clock. The techniques may further include determining if the clock offset is valid (e.g., based on detection of perturbing events or difference between a clock's times). | 07-05-2012 |
Patent application number | Description | Published |
20090172433 | Powering on devices via intermediate computing device - Methods and apparatus relating to powering on devices via an intermediate computing device are described. In an embodiment, a request for data by a first device may be detected at a second device. The second device may determine a third device that stores the requested data and cause it to be turned on if the third device is in a reduced power consumption state. Other embodiments are also disclosed. | 07-02-2009 |
20100011167 | Heterogeneous processors sharing a common cache - A multi-core processor providing heterogeneous processor cores and a shared cache is presented. | 01-14-2010 |
20100125645 | PROVIDING AGGREGATED DIRECTORY STRUCTURE - In an embodiment, circuitry residing, at least in part, at a first network node may initiate, at least in part, replicating, at least in part, at the first node of a file space at a second network node, may detect, at least in part, modification at the second node of the file space, and may initiate, at least in part, corresponding modification at the first node of a replication of the file space. The circuitry also may generate, at least in part, an aggregated directory structure including, at least in part, the file space and another file space resident, at least in part, remotely from the second node. The directory structure may be provided, at least in part, to the second node prior, at least in part, to completion of the replicating, at least in part, at the first node of the file space. | 05-20-2010 |
20100250834 | METHOD AND SYSTEM TO PERFORM CACHING BASED ON FILE-LEVEL HEURISTICS - A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved. | 09-30-2010 |
20120215984 | HETEROGENEOUS PROCESSORS SHARING A COMMON CACHE - A multi-core processor providing heterogeneous processor cores and a shared cache is presented. | 08-23-2012 |
20130275681 | CACHING FOR HETEROGENEOUS PROCESSORS - A multi-core processor providing heterogeneous processor cores and a shared cache is presented. | 10-17-2013 |
20130283070 | HOST CONTROLLED IO POWER MANAGEMENT - Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output. | 10-24-2013 |
20130339572 | MULTI-LEVEL MEMORY WITH DIRECT ACCESS - Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system. | 12-19-2013 |
20140197696 | INTERCHANGEABLE POWER AND SIGNAL CONTACTS FOR IO CONNECTORS - Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits. | 07-17-2014 |
20140242927 | UNIVERSAL IO CONNECTOR AND INTERFACE CAPABLE OF BOTH WIRED AND WIRELESS OPERATION - Systems and methods of interconnecting devices may include a connector assembly having a substrate, a set of input/output (IO) contacts, an antenna structure and transceiver logic. In one example, the transceiver logic may process one or more IO signals associated with the antenna structure and process one or more IO signals associated with the set of IO contacts. | 08-28-2014 |
20140281203 | MANAGING DISTURBANCE INDUCED ERRORS - In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells. | 09-18-2014 |
20140317337 | METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH (PCMS) - Methods and apparatus related to management and/or support of metadata for PCMS (Phase Change Memory with Switch) devices are described. In one embodiment, a PCMS controller allows access to a PCMS device based on metadata. The metadata may be used to provide efficiency, endurance, error correction, etc. as discussed in the disclosure. Other embodiments are also disclosed and claimed. | 10-23-2014 |
20150081976 | CACHING FOR HETEROGENEOUS PROCESSORS - A multi-core processor providing heterogeneous processor cores and a shared cache is presented. | 03-19-2015 |