Patent application number | Description | Published |
20120297682 | WINDOW REGULATOR OF VEHICLE - A window regulator assembly of a vehicle may include an actuator, a wire connected to the actuator and actuated by the actuator, an upper pulley and a lower pulley provided in upper and lower positions of a door for guiding movement of the wire, a pulley locking unit provided for mounting the upper pulley and the lower pulley to the door, and a removable support member, wherein the removable support member controls a relative position of the upper pulley and the lower pulley therebetween and may be removed from the upper pulley and the lower pulley after the upper pulley and the lower pulley may be installed on the door. | 11-29-2012 |
20140054903 | 2-STEP GUIDE HOOD LATCH APPARATUS FOR VEHICLE - A 2-step guide hood latch apparatus for a vehicle is provided, which by removing a conventional safety lever, a driver can open a hood merely with two times of manipulation of a release handle indoors without going out of the vehicle, thereby solving the conventional inconvenience of having to put the hand into the hood and manipulate the safety lever. To this end, the 2-step guide hood latch apparatus includes a pawl rotatably mounted on a base plate, a claw rotatably mounted on the base plate in such a way to be held with the pawl, and a guide lever, an end portion of which is hinge-coupled to the pawl by a hinge structure, and a center portion and the other end portion of which are coupled to the claw to induce 1-step lock and 2-step lock states of the claw, in which a hood is opened merely with manipulation of a release lever inside a vehicle. | 02-27-2014 |
20140062098 | TWO STEP LINK HOOD LATCH APPARATUS FOR VEHICLE - A two step link hood latch apparatus for a vehicle allows a hood to be opened only with an operation of a release handle inside a vehicle. The apparatus includes a claw, the pawl, a pivot, and a link. The claw is disposed at a base plate to be rotatable, restrains a hood striker through a stop groove, and is restrained to a pawl through first and second stop ends in first step and second step lock states. The pawl is disposed at the base plate to be rotatable, and restrains the rotation of the claw in steps by using the stop protrusion. The pivot is disposed at the base plate to be rotatable in a hinge structure, and transmits a pulling force generated from the release handle. The link connects the pivot and the pawl and rotates the pawl in linkage with the pivot. | 03-06-2014 |
Patent application number | Description | Published |
20090002435 | NOZZLE CHIP CLEANING APPARATUS OF INKJET PRINTER AND INKJET PRINTER WITH THE SAME - A nozzle chip cleaning apparatus of an inkjet printer with an improved supply/return structure for a cleaning solution for cleaning a nozzle chip includes a flexible bag to hold fluid and to contact a nozzle chip of an inkjet head. A lifting apparatus may move the flexible bag to be in contact with a surface of the nozzle chip. The nozzle chip cleaning apparatus employs a method in which a flexible bag wipes a surface of a nozzle chip cleaning solution. | 01-01-2009 |
20090141084 | IMAGE FORMING APPARATUS - An image forming apparatus that provides an easy installation and separation of a print head thereto and therefrom. The image forming apparatus can include a body, a print head including a nozzle part having a length at least a width as wide as a printable printing medium, a head mount provided at the body to mount the print head, at least one first connector provided at the head mount, and at least one second connector provided at the print head to correspond to the at least one first connector. The first connector and second connector are connected with each other as the print head is mounted to the head mount. | 06-04-2009 |
20090303280 | PRINTING HEAD CLEANING APPARATUS, IMAGE FORMING APPARATUS HAVING THE SAME AND METHOD TO CLEAN PRINTING HEAD - A printing head cleaning apparatus usable with an image forming apparatus includes a spraying unit to spray a quantity of cleaning solution using a sprayer and a cleaning shuttle to carry the spraying unit. The spraying unit includes a cleaning solution tank to store the cleaning solution sprayed by the sprayer, a spraying cam to operate the sprayer to selectively spray a quantity of the cleaning solution, and a cam driving member to cause the spraying cam to rotate according to movement of the cleaning shuttle. | 12-10-2009 |
20100002046 | INKJET IMAGE FORMING APPARATUS - An inkjet image forming apparatus includes a device to protect an ink sensing device operated without use of a separate drive source. The inkjet image forming apparatus includes at least one protecting device having a protecting member to protect the ink sensing device from impurities or to release the ink sensing device from protection, the protecting member being operated in linkage with the maintenance device to thereby be moved between the first position and the second position. | 01-07-2010 |
20110011337 | IMAGE FORMING APPARATUS - An image forming apparatus including a medium feeding unit to supply a print medium, a medium coating assembly to coat the print medium with a coating liquid, and an image forming unit to form an image on the coated print medium, the medium coating assembly including a container to store the coating liquid, a coating unit to coat the print medium with the coating liquid, a channel to guide the coating liquid to move between the container and the coating unit, and a controller to selectively control the coating liquid to be supplied from the container to the coating unit and to be recovered from the coating unit to the container through the same channel. | 01-20-2011 |
20120170948 | Developing device including toner concentration sensor and image forming apparatus including the developing device - A developing device using a two-component developing agent including a toner and a carrier. The developing device includes a toner concentration sensor which detects a concentration of a toner contained in the developing agent within the accommodation unit by using electrostatic capacity. The toner concentration sensor includes a frame combined with a housing that forms the accommodation unit, a measuring groove formed in the frame to be concave with respect to an inner surface of the housing so that the developing agent conveyed by the agitator is flowed into the measuring groove, and a pair of opposite electrodes disposed on the measuring groove. | 07-05-2012 |
20130164048 | COLOR REGISTRATION SENSOR FOR IMAGE FORMING APPARATUS, METHOD OF DETECTING REGISTRATION TEST PATTERNS BY USING THE COLOR REGISTRATION SENSOR, AND IMAGE FORMING APPARATUS INCLUDING THE COLOR REGISTRATION SENSOR - A color registration sensor of an image forming apparatus, and a method of detecting registration test patterns of a plurality of colors formed on a transfer medium, by using the color registration sensor. The color registration sensor detects a current generated by an electric force of a charged toner forming registration test patterns by using an electrode, as the registration test patterns of a plurality of colors formed on the transfer medium approach the color registration sensor, and detects a location of each of the registration test patterns of the plurality of colors by using a voltage signal obtained by converting the detected current. | 06-27-2013 |
20150182090 | ROBOT CLEANER - Disclosed is a robot cleaner capable of reducing the material cost thereof by use of fewer motors, and performing wet cleaning while travelling in all directions and rubbing the floor surface, the robot cleaner includes a plurality of motors generating driving forces, a plurality of pad assemblies configured to rotate by receiving a driving force from one of the plurality of motors, and provided in a tilted manner so that a bottom surface of each of the plurality of pad assemblies has an uneven frictional force with respect to a floor surface, and a tilt gear unit configured to simultaneously vary tilting directions of the plurality of pad assemblies by receiving a driving force from another one of the plurality of motors, wherein the robot clean can travel in all directions depending on a tilting direction and a rotational direction of each of the plurality of pad assemblies. | 07-02-2015 |
Patent application number | Description | Published |
20120208361 | METHOD FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate. | 08-16-2012 |
20140370713 | METHOD OF FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate. | 12-18-2014 |
Patent application number | Description | Published |
20130005088 | METHODS OF FORMING SEMICONDUCTOR MODULES AND SEMICONDUCTOR MODULES FORMED BY THE SAME - Provided are methods of forming semiconductor modules. The method includes forming a high polymer material layer having an adhesive property on a support substrate, adhering a semiconductor chip to the support substrate using the high polymer material layer, bonding the semiconductor chip adhered to the support substrate to a flexible panel, and removing the support substrate. | 01-03-2013 |
20130148312 | TAPE WIRING SUBSTRATE AND CHIP-ON-FILM PACKAGE INCLUDING THE SAME - A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern. | 06-13-2013 |
20130175528 | CHIP ON FILM PACKAGE INCLUDING TEST PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern. | 07-11-2013 |
20130186680 | Tape Film Packages and Methods of Fabricating the Same - A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern. | 07-25-2013 |
20130240917 | SEMICONDUCTOR PACKAGE HAVING A CONDUCTIVE LAYER FOR ELECTROSTATIC DISCHARGE AND DISPLAY DEVICE INCLUDING THE SAME - A semiconductor package is provided. The semiconductor package may include a base film having a first surface and a second surface opposite the first surface, an interconnection pattern on the first surface of the base film, and a ground layer on the second surface of the base film. The semiconductor package may further include a semiconductor chip on the first surface of the base film within the first region and a via contact plug in the second region that penetrates the base film and is configured to electrically connect the interconnection pattern with the ground layer when electrostatic discharge occurs through the via contact plug. | 09-19-2013 |
20130293816 | CHIP-ON-FILM PACKAGE AND DEVICE ASSEMBLY INCLUDING THE SAME - Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate. | 11-07-2013 |
20140054793 | Chip on Film (COF) Substrate, COF Package and Display Device Including the Same - A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film. | 02-27-2014 |
20140246687 | CHIP ON FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME - A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads. | 09-04-2014 |
20140327148 | CHIP ON FILM PACKAGE INCLUDING DISTRIBUTED VIA PLUGS - A chip on film (COF) package includes a film substrate, first leads on a first surface of the film substrate, the first leads having a first length, and second leads on the first surface of the film substrate, the second leads having a second length larger than the first length, first via plugs penetrating the film substrate and connected to first ends of the first leads, and second via plugs penetrating the film substrate and connected to first ends of the second leads, and first connection leads on a second surface of the film substrate facing the first surface, the first connection leads having first ends connected to the first via plugs, and second connection leads on the second surface of the film substrate, the second connection leads having first ends electrically connected to the second via plugs. | 11-06-2014 |
20140328031 | DISPLAY APPARATUS - Provided is a display apparatus. The display apparatus includes a display panel, a flexible circuit film having a rear surface connected to the display panel, and a front surface opposite to the rear surface, the front surface having a chip mounted thereon, and a first lead bonding portion electrically connecting the chip to the display panel. The first lead bonding portion includes a first portion connected to the chip and overlying a portion of the flexible circuit film, a second portion passing through the flexible circuit film, and a third portion disposed between the flexible circuit film and the display panel on the rear surface of the flexible circuit film, where the third portion overlaps the first portion. | 11-06-2014 |
20140367659 | DISPLAY DEVICES - A display device includes a substantially planar semiconductor package. The semiconductor package drives unit display elements of the display device. The semiconductor package is not folded and has a flat structure. Thus, the occurrence of defects and/or errors in the display device may be reduced as compared to display devices including folded non-planar semiconductor packages. As a result, reliability of the display device may be improved. | 12-18-2014 |
20150060931 | SEMICONDUCTOR PACKAGES AND DISPLAY DEVICES INCLUDING SEMICONDUCTOR PACKAGES - Semiconductor packages are provided. A semiconductor package may include a semiconductor chip. The semiconductor package may include a substrate and first and second conductive regions on the substrate. In some embodiments, the substrate may be a flexible substrate, and the first and second conductive regions may be on the same surface of the flexible substrate. Display devices including semiconductor packages are also provided. In some embodiments, a display device may include a flexible substrate that is bent such that first and second conductive regions thereof are connected to each other via an intervening third conductive region. | 03-05-2015 |
20160020196 | CHIP-ON-FILM PACKAGE AND DEVICE ASSEMBLY INCLUDING THE SAME - Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate. | 01-21-2016 |
20160049356 | CHIP-ON-FILM PACKAGE HAVING BENDING PART - A chip-on-film package comprises a film substrate comprising upper and lower surfaces, and a side having a bending part. A first output interconnection formed on the upper surface of the film substrate extends from a semiconductor chip disposed on the upper surface toward the bending part. A second output interconnection includes an upper output interconnection formed on the upper surface of the film substrate, and a lower output interconnection formed on the lower surface and extending onto the bending part. An input interconnection includes an upper input interconnection formed on the upper surface of the film substrate and a lower input interconnection formed on the lower surface and extending away from the bending part. Through-vias are formed to pass through the film substrate and electrically connect the upper output interconnection to the lower output interconnection, and the upper input interconnection to the lower input interconnection. | 02-18-2016 |
20160111299 | Methods of Fabricating Tape Film Packages - A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern. | 04-21-2016 |
Patent application number | Description | Published |
20150337952 | SHIFT CONTROL METHOD FOR DCT VEHICLE - A shift control method for a dual clutch transmission (DCT) vehicle may include, performed by a controller of the DCT, an actual shift determining step, a cooperation control termination determining step, a flare determining step, an engine torque reducing step, a torque adding step, an engine torque raising step, and a shift finishing step of reducing an amount of reduction of the engine torque until synchronization is completed in proportion to a synchronization prediction time in which it takes an engine speed to reach a synchronization speed when the synchronization prediction time is smaller than a reference time during which the torque adding step and the engine torque raising step are performed, and having slip control over an engagement-side clutch. | 11-26-2015 |
20160138713 | SHIFT CONTROL METHOD FOR VEHICLE WITH DCT - A shift control method for a vehicle with a Dual Clutch Transmission (DCT) may include determining whether power-on up-shifting has been initiated, performing torque handover control by controlling release-side and engage-side clutches by repeatedly calculating control torques of the release-side clutch and the engage-side clutch over time, when the power-on up-shifting is started and a torque handover period is entered, determining whether tip-out is generated during the performing of torque handover control, obtaining a remaining updating time by recalculating a remaining time until the end of the torque handover period in accordance with a decrease in engine torque, when it is determined that tip-out has been generated, and controlling the release-side and the engage-side clutches on the basis of the control torques for the release-side and the engage-side clutches that are made different in accordance with the calculated remaining updating time during a remaining torque handover period. | 05-19-2016 |
Patent application number | Description | Published |
20150104946 | METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICES - Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings. | 04-16-2015 |
20150333059 | SEMICONDUCTOR DEVICES INCLUDING ISOLATION GATE LINES BETWEEN ACTIVE PATTERNS AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate having active regions extending in a first direction and separated therealong by a device isolation layer, and conductive word lines extending on the substrate in a second direction intersecting the first direction. Ones of the word lines extending between the active regions define isolation gate lines, which are insulated from the active regions by the device isolation layer. Edges of the active regions adjacent the isolation gate lines respectively include first and second corners that are spaced apart from an adjacent one of the isolation gate lines by substantially equal distances. Related fabrication methods are also discussed. | 11-19-2015 |
20160042965 | METHODS FOR FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns. | 02-11-2016 |
Patent application number | Description | Published |
20100137367 | NOVEL CRYSTALLINE BEPOTASTINE METAL SALT HYDRATE, METHOD FOR PREPARING SAME, AND PHARMACEUTICAL COMPOSITION COMPRISING SAME - The present invention discloses a non-hygroscopic crystalline bepotastine metal salt hydrate, a method for preparing same, and a pharmaceutical composition comprising same for treating or preventing a histamine-mediated disease or an allergic disease. | 06-03-2010 |
20100168433 | PROCESS FOR PREPARING BEPOTASTINE AND INTERMEDIATES USED THEREIN - A process for stereospecific preparation of bepotastine of formula (I) and novel intermediates used therein having formulae (II) to (IV) are provided. The inventive process comprises subjecting (RS)-4-[(4-chlorophenyl)(2-pyridyl)methoxy]piperidine to a reaction with a 4-halobutanoic acid l-menthyl ester, halo being chloro, bromo or iodo, in an organic solvent in the presence of a base to produce (RS)-bepotastine l-menthyl ester of formula (II), conducting a reaction of the compound of formula (II) with N-benzyloxycarbonyl L-aspartic acid in an organic solvent to induce selective precipitation of bepotastine l-menthyl ester.N-benzyloxycarbonyl L-aspartate of formula (III), filtering the precipitates formed in step 2) to isolate the compound of formula (III), treating the compound of formula (III) with a base to liberate bepotastine l-menthyl ester of formula (IV), and hydrolyzing the compound of formula (IV) in the presence of a base. The inventive process can provide bepotastine having a high optical purity of not less than 99.5% in a high yield, and thus, is useful in the development of anti-histamines and anti-allergic agents. | 07-01-2010 |
20130116213 | NOVEL FUSED PYRIMIDINE DERIVATIVES FOR INHIBITION OF TYROSINE KINASE ACTIVITY - The present invention relates to a novel fused pyrimidine derivative having an inhibitory activity for tyrosine kinases, and a pharmaceutical composition for preventing or treating cancers, tumors, inflammatory diseases, autoimmune diseases, or immunologically mediated diseases comprising same as an active ingredient. | 05-09-2013 |
20140364438 | TRIAZOLOPYRIDINE DERIVATIVES AS A TYROSINE KINASE INHIBITOR - Provided is a novel triazolopyridine derivative having irreversible tyrosine kinase inhibiting activities, and a pharmaceutical composition comprising the same which can be useful for prevention or treatment of inflammatory diseases, autoimmune diseases, proliferative diseases or hyperproliferative diseases, immunologically mediated diseases, cancers or tumors. | 12-11-2014 |
20150045324 | NOVEL FUSED PYRIMIDINE DERIVATIVES FOR INHIBITION OF TYROSINE KINASE ACTIVITY - The present invention relates to a novel fused pyrimidine derivative having an inhibitory activity for tyrosine kinases, and a pharmaceutical composition for preventing or treating cancers, tumors, inflammatory diseases, autoimmune diseases, or immunologically mediated diseases comprising same as an active ingredient. | 02-12-2015 |
20150299185 | NOVEL IMIDAZOPYRIDINE DERIVATIVES AS A TYROSINE KINASE INHIBITOR - Provided is a novel imidazopyridine derivative having irreversible tyrosine kinase inhibiting activities, and a pharmaceutical composition comprising the same which can be useful for prevention or treatment of inflammatory diseases, autoimmune diseases, proliferative diseases or hyperproliferative diseases, immunologically mediated diseases, cancers or tumors. | 10-22-2015 |
Patent application number | Description | Published |
20090057644 | Phase-change memory units, methods of forming the phase-change memory units, phase-change memory devices having the phase-change memory units and methods of manufacturung the phase-change memory devices - A phase-change memory unit includes a lower electrode on a substrate, a phase-change material layer pattern including germanium-antimony-tellurium (GST) and carbon on the lower electrode, a transition metal layer pattern on the phase-change material layer pattern, and an upper electrode on the first transition metal layer pattern. The phase-change memory unit may have good electrical characteristics. | 03-05-2009 |
20090243117 | CONTACT STRUCTURE, A SEMICONDUCTOR DEVICE EMPLOYING THE SAME, AND METHODS OF MANUFACTURING THE SAME - A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern. | 10-01-2009 |
20100144135 | Method of manufacturing a phase changeable memory unit - A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer. | 06-10-2010 |
20100176365 | RESISTANCE VARIABLE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A resistance variable memory device includes at least one bottom electrode, a first insulating layer containing a trench which exposes the at least one bottom electrode, and a resistance variable material layer including respective first and second portions located on opposite sidewalls of the trench, respectively, where the first and second portions of the resistance variable material layer are electrically connected to the at least one bottom electrode. The device further includes a protective layer covering the resistance variable material layer within the trench, and a second insulating layer located within the trench and covering the protective layer within the trench | 07-15-2010 |
20110291066 | Nonvolatile Memory Devices Having Cells with Oxygen Diffusion Barrier Layers Therein and Methods of Manufacturing the Same - A nonvolatile memory cell includes first and second electrodes and a data storage layer extending between the first and second electrodes. An oxygen diffusion barrier layer is provided, which extends between the data storage layer and the first electrode. An oxygen gettering layer is also provided, which extends between the oxygen diffusion barrier layer and the data storage layer. The oxygen diffusion barrier layer includes aluminum oxide, the oxygen gettering layer includes titanium, the data storage layer includes a metal oxide, such as magnesium oxide, and at least one of the first and second electrodes includes a material selected from a group consisting of tungsten, polysilicon, aluminum, titanium nitride silicide and conductive nitrides. | 12-01-2011 |
20130234100 | NONVOLATILE MEMORY CELLS HAVING PHASE CHANGEABLE PATTERNS THEREIN FOR DATA STORAGE - Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction. | 09-12-2013 |
20140374840 | SEMICONDUCTOR DEVICES USING MOS TRANSISTORS WITH NONUNIFORM GATE ELECTRODE STRUCTURES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width. | 12-25-2014 |
20150270177 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor. | 09-24-2015 |