Patent application number | Description | Published |
20090253944 | Process for Preparing Alkylene Oxides - The invention provides a process for preparing ethylene oxide and/or propylene oxide by contacting ethylene and/or propylene with an oxidizing agent, wherein (i) the reaction takes place in a microreaction system (p-reactor) and (ii) the oxidizing agent used is a peroxo compound. | 10-08-2009 |
20100009063 | Process for the preparation of active substance concentrate - Disclosed is a process for the preparation of active substance concentrates, which is distinguished in that an active-substance-containing starting material,
| 01-14-2010 |
20100041923 | Method for Producing Alkylene Oxide Addition Products - The invention relates to a method for producing alkylene oxide addition products by reaction of compounds having a nucleophilic center with alkylene oxides in a reactor having a large inner surface. The invention is characterized in that the reaction is carried out exclusively in the liquid phase. | 02-18-2010 |
20100234458 | Process for the Production of Fatty Acid Alkyl Esters - Disclosed is an improved process for the production of fatty acid lower alkyl esters according to formula (I) | 09-16-2010 |
20100285557 | Efficient Astaxanthin Production Strains Derived from Haematococcus Pluvialis - The present invention pertains to a method for the efficient production of carotenoids. In particular, the present invention is directed to a method for producing carotenoid and carotenoid-containing cells, especially astaxanthin and astaxanthin-containing cells, by generating mutant microorganisms belonging to the photoautotrophic algae of the Class Chlorophyceae and culturing same. The present invention further relates to methods of generating microorganisms producing high yields of carotenoids, in particular astaxanthin, products containing said microorganisms or said carotenoids, and the use of said carotenoids produced by the microorganisms according to the present invention and deposited mutant strains generated from said microorganisms. | 11-11-2010 |
20110089370 | Lipophilic Preparations - Disclosed are novel lipophilic preparations comprising (a) from 20 to 40% by weight of myristic acid or esters thereof, (b) from 20 to 40% by weight of palmitic acid or esters thereof, (c) from 0.1 to 5% by weight of aliphatic and/or cycloaliphatic hydrocarbons and (d) less than 20% by weight of carboxylic acids or esters thereof having 12 and fewer carbons in the acyl moiety and (e) less than 20% by weight of carboxylic acids or esters thereof having 16 and more carbons in the acyl moiety, with the proviso that all percentages add up to 100% by weight. | 04-21-2011 |
20110218349 | Method for Producing Alkylene Oxide Addition Products - The invention relates to a method for producing alkylene oxide addition products. The method according to the invention is characterized by (a) contacting ethylene and/or propylene with an oxidizing agent in a first structured reactor (“μ reactor”) and (b) feeding the ethylene oxide and/or propylene oxide so obtained, optionally after purification, to a second structured reactor where it is reacted with a compound having a nucleophilic molecular group. | 09-08-2011 |
20140303393 | Process For Preparing Sulfates And/Or Sulfonates In A Micro-Reaction System - Suggested is a process for preparing sulfates and/or sulfonates by adding sulfur trioxide to a compound comprising at least one hydroxyl function and/or at least one double bond, which is characterized in that
| 10-09-2014 |
Patent application number | Description | Published |
20080285344 | Integrated Circuits; Methods for Manufacturing an Integrated Circuit; Memory Modules; Computing Systems - Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems. | 11-20-2008 |
20090282308 | Memory Cell Arrangement and Method for Reading State Information From a Memory Cell Bypassing an Error Detection Circuit - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, at least one error detection circuit, and a controller configured to control a read operation to read state information from the at least one memory cell by reading a memory cell state information bypassing the at least one error correction circuit, or by reading the memory cell state information and supplying it to the at least one error correction circuit. | 11-12-2009 |
20100002503 | Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell. | 01-07-2010 |
20100020610 | Integrated Circuits Having a Controller to Control a Read Operation and Methods for Operating the Same - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a memory cell block having a plurality of memory cells, a storage portion configured to store information about a quality characteristic of the memory cells of the memory cell block, and a controller configured to control a read operation, and to change the information about the quality characteristic depending on a quality of a read operation. | 01-28-2010 |
Patent application number | Description | Published |
20100006983 | PROCESS FOR PRODUCING SUBLITHOGRAPHIC STRUCTURES - A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures | 01-14-2010 |
20110248234 | VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer. | 10-13-2011 |
20120305873 | VERTICAL INTERCONNECT STRUCTURE, MEMORY DEVICE AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer. | 12-06-2012 |