Patent application number | Description | Published |
20140273310 | MONITORING PATTERN FOR DEVICES - Reticle and methods for forming a device or reticle are presented. A reticle is provided with a device pattern and a first monitoring pattern. The first monitoring pattern includes a plurality of first test cells having a first test cell area and a first test pattern. The first test cells have different first pitch ratios to an anchor pitch and the first test pattern fills the first test cell area of a first test cell. A wafer with a resist layer is exposed with a lithographic system using the reticle. The resist is developed to form a patterned resist layer on the wafer and the wafer is processed using the patterned resist layer. | 09-18-2014 |
20150028482 | DEVICE LAYOUT FOR REDUCING THROUGH-SILICON-VIA STRESS - Approaches for reducing through-silicon via (TSV) stress are provided. Specifically, provided is a device comprising a substrate and a TSV formed in the substrate, the TSV having an element patterned therein. The TSV further comprises a set of openings adjacent the element that are subsequently filled with a TSV fill material. The element may be patterned according to any number of shapes (e.g., circle, oval, rectangle, etc.) to optimize the stress distribution for the TSV. The element is patterned and provided within the TSV in order to reduce or compensate for stress forces caused by a change in volume of the conductive fill materials of the openings of the TSV. These approaches apply to both single TSVs and a plurality of TSVs (e.g., arranged as a matrix). | 01-29-2015 |
20150028500 | FORMING ALIGNMENT MARK AND RESULTING MARK - Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry. | 01-29-2015 |
20150192866 | EFFICIENT OPTICAL PROXIMITY CORRECTION REPAIR FLOW METHOD AND APPARATUS - A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process. | 07-09-2015 |
20150287651 | OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION - A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer. | 10-08-2015 |
20150310157 | MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION - Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio. | 10-29-2015 |
20160079180 | OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION - A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer. | 03-17-2016 |
20160124308 | ALTERNATING SPACE DECOMPOSITION IN CIRCUIT STRUCTURE FABRICATION - Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material. | 05-05-2016 |
20160125121 | ACHIEVING A CRITICAL DIMENSION TARGET BASED ON RESIST CHARACTERISTICS - Achieving a critical dimension target for a feature based on characteristics of a resist is facilitated. Mask data is established for fabricating a lithographic mask to expose different regions of a resist to high, low, and intermediate exposure levels. The resist is configured to exhibit high solubility when exposed to the high or low exposure level, and low solubility when exposed to the intermediate exposure level. A critical dimension for a region of the resist to be exposed to the intermediate exposure level is determined, and the mask data is established to indicate opaque regions for forming on the lithographic mask. The opaque regions are arrayed to facilitate exposing the region of the resist to the intermediate exposure level, to achieve the determined critical dimension. Further, a method is provided for forming in-situ a patterned mask from a mask layer above a substrate material. | 05-05-2016 |