Patent application number | Description | Published |
20150070570 | Adaptive Auto Exposure and Dynamic Range Compensation - This disclosure pertains to systems, methods, and computer readable media for extending the dynamic range of images using an operation referred to herein as “Adaptive Auto Exposure” (AAE). According to the embodiments disclosed herein, the AAE-enabled higher dynamic range capture operations are accomplished without blending multiple or bracketed exposure captures (as is the case with traditional high dynamic range (HDR) photography). AAE also enables high signal-to-noise ratio (SNR) rendering when scene content allows for it and/or certain highlight clipping is tolerable. Decisions with regard to preferred AE strategies may be based, at least in part, on one or more of the following: sensor characteristics; scene content; and pre-defined preferences under different scenarios. | 03-12-2015 |
20150103135 | Compositing Pairs Of Image Frames From Different Cameras Of A Mobile Device To Generate A Video Stream - Some embodiments provide a novel method for in-conference adjustment of encoded video pictures captured by a mobile device having at least first and second cameras. The method may involve real-time modifications of composite video displays that are generated by the mobile devices involved in such a conference. Specifically, in some embodiments, the mobile devices generate composite displays that simultaneously display multiple videos captured by multiple cameras of one or more devices. In some cases, the composite displays place the videos in adjacent display areas (e.g., in adjacent windows). In other cases, the composite display is a picture-in-picture (PIP) display that includes at least two display areas that show two different videos where one of the display areas is a background main display area and the other is a foreground inset display area that overlaps the background main display area. | 04-16-2015 |
20150243243 | SERVER-SIDE ADAPTIVE VIDEO PROCESSING - Adaptive video processing for a target display panel may be implemented in or by a server/encoding pipeline. The adaptive video processing methods may obtain and take into account video content and display panel-specific information including display characteristics and environmental conditions (e.g., ambient lighting and viewer location) when processing and encoding video content to be streamed to the target display panel in an ambient setting or environment. The server-side adaptive video processing methods may use this information to adjust one or more video processing functions as applied to the video data to generate video content in the color gamut and dynamic range of the target display panel that is adapted to the display panel characteristics and ambient viewing conditions. | 08-27-2015 |
20150245043 | DISPLAY-SIDE ADAPTIVE VIDEO PROCESSING - Adaptive video processing for a target display panel may be implemented in or by a decoding/display pipeline associated with the target display panel. The adaptive video processing methods may take into account video content, display characteristics, and environmental conditions including but not limited to ambient lighting and viewer location when processing and rendering video content for a target display panel in an ambient setting or environment. The display-side adaptive video processing methods may use this information to adjust one or more video processing functions as applied to the video data to render video for the target display panel that is adapted to the display panel according to the ambient viewing conditions. | 08-27-2015 |
20150245044 | BACKWARD-COMPATIBLE VIDEO CAPTURE AND DISTRIBUTION - Video processing techniques and pipelines that support capture, distribution, and display of high dynamic range (HDR) image data to both HDR-enabled display devices and display devices that do not support HDR imaging. A sensor pipeline may generate standard dynamic range (SDR) data from HDR data captured by a sensor using tone mapping, for example local tone mapping. Information used to generate the SDR data may be provided to a display pipeline as metadata with the generated SDR data. If a target display does not support HDR imaging, the SDR data may be directly rendered by the display pipeline. If the target display does support HDR imaging, then an inverse mapping technique may be applied to the SDR data according to the metadata to render HDR data for display. Information used in performing color gamut mapping may also be provided in the metadata and used to recover clipped colors for display. | 08-27-2015 |
Patent application number | Description | Published |
20100225655 | Concurrent Encoding/Decoding of Tiled Data - Example embodiments of the present disclosure provide techniques for dividing bitmaps into tiles and processing the tiles concurrently using multiple tile engines. Data compression algorithms may be adapted so that the algorithms can be concurrently processed by multiple data slice engines. The algorithms may be further adapted so that the concurrent outputs for each stage may be passed to the next processing stage without delays or dead cycles. The reduction or elimination of delays or dead cycles may result in a lower latency. | 09-09-2010 |
20100226441 | Frame Capture, Encoding, and Transmission Management - Example embodiments of the present disclosure provide techniques for improving the rendering and management of client desktops and the subsequent transmission to the remote client. The techniques may minimize the movement of frame data within the server, the amount of data to be compressed, the amount of data transmitted over the network, and the amount of data to be decompressed. Various embodiments are disclosed for merging rendering functions and encoding functions onto the same chip so that frame data does not need to be transferred, calculation of a tile-based checksum for determining which tiles have changed from frame to frame, the dropping of tiles waiting to be transmitted if network bandwidth or decode speed is limiting the transmission and an equivalent tile in a subsequent frame is available to replace it, and the transfer of the frame buffer into the chip from an external GPU using one of three modes. | 09-09-2010 |
20100231599 | Frame Buffer Management - Disclosed are methods and systems for tracking which data tiles have changed within an image frame. In an embodiment, each cell of a tile change list buffer may contain a frame number and updated when a tile is received from encoder. The frame number may be used as a base pointer for a particular frame buffer. When a frame is decoded, the contents of the tile change list buffer may be copied from the current tile change list buffer to the next buffer. This process may reduce memory traffic because the unchanged tile data does not have to be copied from frame to frame. | 09-16-2010 |
Patent application number | Description | Published |
20080243761 | METHOD AND SYSTEM FOR QUANTIFYING A DATA PAGE REPETITION PATTERN FOR A DATABASE INDEX IN A DATABASE MANAGEMENT SYSTEM - A method and system are presented for quantifying a data page repetition pattern for a database index in a database management system. In one embodiment, the method includes identifying a database index to provide a basis for collecting a data page repetition statistic, the database index having a database index key. The method may also include collecting the data page repetition statistic based on the database index key, wherein the data page repetition statistic quantifies a data page repetition pattern associated with database queries that reference sequential entries of the database index. The method may further include optimizing a data page access process based on the data page repetition statistic. In a further embodiment, the method may utilize both cluster ratio and data page repetition statistics to evaluate data page I/O and CPU cost. | 10-02-2008 |
20140108378 | TECHNIQUE FOR FACTORING UNCERTAINTY INTO COST-BASED QUERY OPTIMIZATION - A technique for factoring uncertainty into cost-based query optimization includes: determining the degree of uncertainty involved in the cost estimates for the query, determining the degree of sensitivity the query has to that uncertainty, and determining if there is an access path that performs well across the range of possible conditions that could occur at execution time, reducing the risk of performance spikes and performance volatility. If such an access path exists, select that access path; if not, perform parametric query optimization or query re-optimization. | 04-17-2014 |
20140214797 | TECHNIQUE FOR FACTORING UNCERTAINTY INTO COST-BASED QUERY OPTIMIZATION - A technique for factoring uncertainty into cost-based query optimization includes: determining the degree of uncertainty involved in the cost estimates for the query, determining the degree of sensitivity the query has to that uncertainty, and determining if there is an access path that performs well across the range of possible conditions that could occur at execution time, reducing the risk of performance spikes and performance volatility. If such an access path exists, select that access path; if not, perform parametric query optimization or query re-optimization. | 07-31-2014 |
20150339350 | DATA-PARTITIONED SECONDARY INDEX (DPSI) PARTITION LEVEL JOIN - Provided are techniques for a Data-Partitioned Secondary Index (DPSI) partition level join. While using a Data-Partitioned Secondary Index (DPSI) to perform a join of an outer table and an inner table, a different task from multiple tasks is assigned to each partition of the inner table. With each task, a join is performed of the outer table and the assigned partition of the inner table using the DPSI to generate results. The results from each different task are merged. | 11-26-2015 |
Patent application number | Description | Published |
20090315079 | Layout Architecture for Improving Circuit Performance - An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight. | 12-24-2009 |
20100078725 | Standard Cell without OD Space Effect in Y-Direction - An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region. | 04-01-2010 |
20100127333 | NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT - The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate. | 05-27-2010 |
20100164614 | Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules - An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell. | 07-01-2010 |
20100281446 | Integrated Circuit Design using DFM-Enhanced Architecture - Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell. | 11-04-2010 |
20110291197 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance. | 12-01-2011 |
20110291200 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure. | 12-01-2011 |
20120240088 | SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS - A method of designing an integrated circuit includes defining at least one dummy layer covering at least one of a portion of a first metallic layer and a portion of a second metallic layer of an integrated circuit. The second metallic layer is disposed over the first metallic layer. The first metallic layer, the second metallic layer and a gate electrode of the integrated circuit have a same routing direction. A logical operation is performed to a file corresponding to the at least one of the portion of the first metallic layer and the portion of the second metallic layer covered by the dummy layer so as to size at least one of the portion of the first metallic layer and the portion of the second metallic layer. | 09-20-2012 |
20130093052 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A RESISTOR AND METHOD OF FORMING THE SAME - The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures. | 04-18-2013 |
20130113537 | PULSE GENERATOR - A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal. | 05-09-2013 |
20130119449 | SEMICONDUCTOR DEVICE WITH SEAL RING WITH EMBEDDED DECOUPLING CAPACITOR - A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to V | 05-16-2013 |
20130130456 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region. | 05-23-2013 |
20140183632 | Contact Structure Of Semiconductor Device - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance. | 07-03-2014 |
20140252477 | FinFET with an Asymmetric Source/Drain Structure and Method of Making Same - Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width. | 09-11-2014 |
20140332859 | Self-Aligned Wrapped-Around Structure - An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first portion of the spacer, etching away an unprotected portion of the structure layer disposed outside a periphery collectively defined by the spacer and the photoresist to form a structure having a footer portion and a non-footer portion, the non-footer portion and the footer portion collectively encircling the semiconductor column, and removing the photoresist and the spacer. | 11-13-2014 |
20150048441 | SEMICONDUCTOR ARRANGEMENT WITH ONE OR MORE SEMICONDUCTOR COLUMNS - A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm. | 02-19-2015 |
20150060996 | SEMICONDUCTOR DEVICE WITH SILICIDE - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region. | 03-05-2015 |
20150069475 | SEMICONDUCTOR DEVICE WITH REDUCED ELECTRICAL RESISTANCE AND CAPACITANCE - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance. | 03-12-2015 |
Patent application number | Description | Published |
20090004370 | Metal Inks, Methods of Making the Same, and Methods for Printing and/or Forming Metal Films - Printable metal formulations, methods of making the formulations, and methods of coating or printing thin films from metal ink precursors are disclosed. The metal formulation generally includes one or more Group 4, 5, 6, 7, 8, 9, 10, 11, or 12 metal salts or metal complexes, one or more solvents adapted to facilitate coating and/or printing of the formulation, and one or more optional additives that form (only) gaseous or volatile byproducts upon reduction of the metal salt or metal complex to an elemental metal and/or alloy thereof. The formulation may be made by combining the metal salt(s) or metal complex(es) and the solvent(s), and dissolving the metal salt(s) or metal complex(es) in the solvent(s) to form the formulation. Thin films may be made by coating or printing the metal formulation on a substrate; removing the solvents to form a metal-containing precursor film; and reducing the metal-containing precursor film. | 01-01-2009 |
20100022078 | Aluminum Inks and Methods of Making the Same, Methods for Depositing Aluminum Inks, and Films Formed by Printing and/or Depositing an Aluminum Ink - Aluminum metal ink compositions, methods of forming such compositions, and methods of forming aluminum metal layers and/or patterns are disclosed. The ink composition includes an aluminum metal precursor and an organic solvent. Conductive structures may be made using such ink compositions by printing or coating the aluminum precursor ink on a substrate (decomposing the aluminum metal precursors in the ink) and curing the composition. The present aluminum precursor inks provide aluminum films having high conductivity, and reduce the number of inks and printing steps needed to fabricate printed, integrated circuits. | 01-28-2010 |
20110178321 | Dopant Group-Substituted Semiconductor Precursor Compounds, Compositions Containing the Same, and Methods of Making Such Compounds and Compositions - Dopant-group substituted (cyclo)silane compounds, liquid-phase compositions containing such compounds, and methods for making the same. Such compounds (and/or ink compositions containing the same) are useful for printing or spin coating a doped silane film onto a substrate that can easily be converted into a doped amorphous or polycrystalline silicon film suitable for electronic devices. Thus, the present invention advantageously provides commercial qualities and quantities of doped semiconductor films from a doped “liquid silicon” composition. | 07-21-2011 |
20110197783 | Doped Polysilanes, Compositions Containing the Same, Methods for Making the Same, and Films Formed Therefrom - Doped polysilanes, inks containing the same, and methods for their preparation and use are disclosed. The doped polysilane generally has the formula H-[A | 08-18-2011 |
20130026453 | Methods of Polymerizing Silanes and Cyclosilanes Using N-Heterocyclic Carbenes, Metal Complexes Having N-Heterocyclic Carbene Ligands, and Lanthanide Compounds - Compositions and methods for controlled polymerization and/or oligomerization of silane (and optionally cyclosilane) compounds, including those of the general formulae Si | 01-31-2013 |
20130344301 | PRINT PROCESSING FOR PATTERNED CONDUCTOR, SEMICONDUCTOR AND DIELECTRIC MATERIALS - Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material. | 12-26-2013 |
20140001405 | Highly Luminescent Nanostructures and Methods of Producing Same | 01-02-2014 |
20150232756 | HIGHLY LUMINESCENT NANOSTRUCTURES AND METHODS OF PRODUCING SAME - Highly luminescent nanostructures, particularly highly luminescent quantum dots, are provided. The nanostructures have high photoluminescence quantum yields and in certain embodiments emit light at particular wavelengths and have a narrow size distribution. The nanostructures can comprise ligands, including C5-C8 carboxylic acid ligands employed during shell formation and/or dicarboxylic or polycarboxylic acid ligands provided after synthesis. Processes for producing such highly luminescent nanostructures are also provided, including methods for enriching nanostructure cores with indium and techniques for shell synthesis. | 08-20-2015 |
20150236195 | HIGHLY LUMINESCENT NANOSTRUCTURES AND METHODS OF PRODUCING SAME - Highly luminescent nanostructures, particularly highly luminescent quantum dots, are provided. The nanostructures have high photoluminescence quantum yields and in certain embodiments emit light at particular wavelengths and have a narrow size distribution. The nanostructures can comprise ligands, including C5-C8 carboxylic acid ligands employed during shell formation and/or dicarboxylic or polycarboxylic acid ligands provided after synthesis. Processes for producing such highly luminescent nanostructures are also provided, including methods for enriching nanostructure cores with indium and techniques for shell synthesis. | 08-20-2015 |