Patent application number | Description | Published |
20080308947 | Die offset die to die bonding - A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate. | 12-18-2008 |
20090091043 | Die offset die to die bonding - A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate. | 04-09-2009 |
20090093084 | Die offset die to bonding - A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate. | 04-09-2009 |
20090115033 | Reduction of package height in a stacked die configuration - A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material. | 05-07-2009 |
20110316158 | METHOD AND SYSTEM FOR THIN MULTI CHIP STACK PACKAGE WITH FILM ON WIRE AND COPPER WIRE - A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die. | 12-29-2011 |
20120038059 | STITCH BUMP STACKING DESIGN FOR OVERALL PACKAGE SIZE REDUCTION FOR MULTIPLE STACK - A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond. | 02-16-2012 |
Patent application number | Description | Published |
20090052092 | Perpendicular magnetic recording head laminated with AFM-FM phase change material - A PMR writer is disclosed that minimizes pole erasure during non-writing and maximize write field during writing through an AFM-FM phase change material that is in an AFM state during non-writing and switches to a FM state by heating during writing. The main pole layer including the write pole may be comprised of a laminated structure having a plurality of “n” ferromagnetic layers and “n-1” AFM-FM phase change material layers arranged in an alternating manner. The AFM-FM phase change material is preferably a FeRh or FeRhX alloy (X=Pt, Pd, or Ir) having a Rh content >35 atomic %. AFM-FM phase change material may also be used as a flux gate to prevent yoke flux from leaking into the write pole tip. Heating for the AFM to FM transition is provided by write coils and/or a coil located near the AFM-FM phase change material to enable faster transition times. | 02-26-2009 |
20090116145 | Perpendicular shield pole writer with tapered main pole and tapered non-magnetic top shaping layer - A PMR writer with a tapered main pole layer and tapered non-magnetic top-shaping layer is disclosed that minimizes trailing shield saturation. A second non-magnetic top shaping layer may be employed to reduce the effective TH size while the bulk of the trailing shield is thicker to allow a larger process window for back end processing. A sloped surface with one end at the ABS and a second end 0.05 to 0.3 microns from the ABS is formed at a 10 to 80 degree angle to the ABS and includes a sloped surface on the upper portion of the main pole layer and on the non-magnetic top shaping layer. An end is formed on the second non-magnetic top shaping layer at the second end of the sloped surface followed by forming a conformal write gap layer and then depositing the trailing shield on the write gap layer and along the ABS. | 05-07-2009 |
20110308074 | Perpendicular magnetic recording head laminated with AFM-FM phase change material - A PMR writer is disclosed that minimizes pole erasure during non-writing and maximize write field during writing through an AFM-FM phase change material that is in an AFM state during non-writing and switches to a FM state by heating during writing. The main pole layer including the write pole may be comprised of a laminated structure having a plurality of “n” ferromagnetic layers and “n−1” AFM-FM phase change material layers arranged in an alternating manner. The AFM-FM phase change material is preferably a FeRh or FeRhX alloy (X=Pt, Pd, or Ir) having a Rh content>35 atomic %. AFM-FM phase change material may also be used as a flux gate to prevent yoke flux from leaking into the write pole tip. Heating for the AFM to FM transition is provided by write coils and/or a coil located near the AFM-FM phase change material to enable faster transition times. | 12-22-2011 |
20120087042 | Perpendicular magnetic recording head laminated with AFM-FM phase change material - A PMR writer is disclosed that minimizes pole erasure during non-writing and maximize write field during writing through an AFM-FM phase change material that is in an antiferromagnetic (AFM) state during non-writing and switches to a ferromagnetic (FM) state by heating during writing. The main pole layer including the write pole may be comprised of a laminated structure having a plurality of “n” ferromagnetic layers and “n−1” AFM-FM phase change material layers arranged in an alternating manner. The AFM-FM phase change material is preferably a FeRh, FeRhPt, FeRhPd, or FeRhIr and may also be used as a flux gate to prevent yoke flux from leaking into the write pole tip. Heating for the AFM to FM transition is provided by write coils and/or a coil located near the AFM-FM phase change material to enable faster transition times. | 04-12-2012 |
20120281313 | Perpendicular Shield Pole Writer with Tapered Main Pole and Tapered Non-Magnetic Top Shaping Layer - A PMR writer with a tapered main pole layer and tapered non-magnetic top-shaping layer is disclosed that minimizes trailing shield saturation. A second non-magnetic top shaping layer may be employed to reduce the effective TH size while the bulk of the trailing shield is thicker to allow a larger process window for back end processing. A sloped surface with one end at the ABS and a second end 0.05 to 0.3 microns from the ABS is formed at a 10 to 80 degree angle to the ABS and includes a sloped surface on the upper portion of the main pole layer and on the non-magnetic top shaping layer. An end is formed on the second non-magnetic top shaping layer at the second end of the sloped surface followed by forming a conformal write gap layer and then depositing the trailing shield on the write gap layer and along the ABS. | 11-08-2012 |
Patent application number | Description | Published |
20140014617 | Method of Forming a Non-Uniform Write Gap Perpendicular Writer for Shingle Writing - A method of forming a PMR writer is disclosed wherein at least one of a recessed center section in the write pole trailing edge and a center recessed trailing shield is used to improve the field gradient at track edge. In all embodiments, there is a non-uniform write gap formed between the trailing edge and the trailing shield. The recessed portion of the write pole trailing edge and/or center recess of the trailing shield has a thickness from 10 to 40 nm in a down-track direction and a width in a cross-track direction of 20 to 200 nm. The distance between the center recess and a corner of the trailing edge is from 20 to 80 nm. A sequence of steps is provided to fabricate the two embodiments of the present invention. | 01-16-2014 |
20140016232 | Non-Uniform Write Gap Perpendicular Writer for Shingle Writing - A PMR writer is disclosed that includes at least one of a recessed center section in the write pole trailing edge and a center recessed trailing shield to improve the field gradient at track edge. In all embodiments, there is a non-uniform write gap between the trailing edge and the trailing shield. The recessed portion of the write pole trailing edge and/or center recess of the trailing shield has a thickness from 10 to 40 nm in a down-track direction and a width in a cross-track direction of 20 to 200 nm. The distance between the center recess and a corner of the trailing edge is from 20 to 80 nm. A sequence of steps is provided to fabricate the two embodiments of the present invention. | 01-16-2014 |
20140307348 | High Data Rate Writer Design - A magnetic write head is fabricated with its main pole attached to and magnetically coupled to a tapered yoke. The tapered yoke can be a top yoke (on the trailing side of the pole), a bottom yoke (on the leading side of the pole) or a combination of top and bottom configurations. The tapered portion of the yoke is at the distal end of the yoke and it is an extension of an otherwise uniformly thick yoke. It is found that the taper enables the yoke to be close to the ABS for better response times and a high data rate, while simultaneously being distant, producing less field disturbance by the shields and corresponding improvement of BER, and ATE/WATE. A taper of 45° is optimal for its production of uniform magnetization of the pole and optimal response times. | 10-16-2014 |
20160055868 | MULTIPLE-INPUT-MULTIPLE-OUTPUT SENSOR DESIGNS FOR MAGNETIC APPLICATIONS - According to one embodiment, a system includes a leading magnetic shield, a first sensor structure above the leading magnetic shield, a first middle magnetic shield above the first sensor structure, a nonmagnetic spacer above the first middle magnetic shield, a second middle magnetic shield above the nonmagnetic spacer, a second sensor structure above the second middle magnetic shield, and a trailing magnetic shield above the second sensor structure. Other systems, methods, and computer program products are described in additional embodiments. | 02-25-2016 |
Patent application number | Description | Published |
20080254208 | Thin film magnetic head structure adapted to manufacture a thin film magnetic head - A thin-film magnetic head structure has a configuration adapted to manufacture a thin-film magnetic head configured such that a main magnetic pole layer including a magnetic pole end part on a side of a medium-opposing surface opposing a recording medium, a write shield layer opposing the magnetic pole end part so as to form a recording gap layer on the medium-opposing surface side, and a thin-film coil wound about the write shield layer or main magnetic pole layer are laminated. The main magnetic pole layer has an end face joint structure where respective end faces of the magnetic pole end part and a yoke magnetic pole part having a size greater than that of the magnetic pole end part are joined to each other, and a surface with a flat structure on a side closer to the thin-film coil. | 10-16-2008 |
20080316653 | Magnetic head for perpendicular magnetic recording and method of manufacturing same - A magnetic head includes: a pole layer; a nonmagnetic layer disposed on part of the top surface of the pole layer; a gap layer disposed on the pole layer and the nonmagnetic layer; and a shield disposed on the gap layer. The top surface of the pole layer includes: a first portion having a first edge located in a medium facing surface and a second edge opposite thereto; and a second portion located farther from the medium facing surface than the first portion and connected to the first portion at the second edge. The first portion is inclined with respect to a direction orthogonal to the medium facing surface so that the distance from a substrate increases with increasing distance from the medium facing surface. The nonmagnetic layer has a bottom surface touching the second portion, and this bottom surface has an edge located at the second edge. | 12-25-2008 |
20090017198 | Thin-film magnetic head, method of manufacturing the same, head Gimbal assembly, and hard disk drive - A thin-film magnetic head has a laminated construction comprising a main pole layer having a magnetic pole tip on a side of the medium-opposing surface opposing a recording medium, a write shield layer opposing the magnetic pole tip forming a recording gap layer, on the side of the medium-opposing surface, and a thin-film coil wound around at least a portion of the write shield layer. The thin-film magnetic head has an upper yoke pole layer having a larger size than the portion of the main pole layer which is more distant from the medium-opposing surface than the recording gap layer, wherein the upper yoke pole layer is joined to the side of the main pole layer which is near the thin-film coil. | 01-15-2009 |
20090201611 | Perpendicular write head with tapered main pole - Prior art designs of single pole writers have been limited by premature saturation at the tip. This limits the head field that can be achieved without simultaneously widening the write profile. This problem has bee solved by means of a vertical main pole whose thickness has its conventional value a short distance from the tip but that tapers down to a significantly reduced value as it approaches the tip. A process for manufacturing this tapered tip design is also presented. | 08-13-2009 |
20090202728 | Perpendicular write head with tapered main pole - Prior art designs of single pole writers have been limited by premature saturation at the tip. This limits the head field that can be achieved without simultaneously widening the write profile. This problem has bee solved by means of a vertical main pole whose thickness has its conventional value a short distance from the tip but that tapers down to a significantly reduced value as it approaches the tip. A process for manufacturing this tapered tip design is also presented. | 08-13-2009 |
20090207525 | Perpendicular write head with tapered main pole - Prior art designs of single pole writers have been limited by premature saturation at the tip. This limits the head field that can be achieved without simultaneously widening the write profile. This problem has bee solved by means of a vertical main pole whose thickness has its conventional value a short distance from the tip but that tapers down to a significantly reduced value as it approaches the tip. A process for manufacturing this tapered tip design is also presented. | 08-20-2009 |
20120257305 | PMR WRITE HEAD WITH ASSISTED MAGNETIC LAYER - A PMR writer is disclosed wherein a magnetic assist layer (MAL) made of an anisotropic (−Ku) or (+Ku) magnetic material is formed along a main pole trailing side to optimize the vertical magnetic field and field gradient at the air bearing surface. A Ru seed layer is formed between the main pole and (−Ku) MAL to induce a hard axis direction toward the main pole. A (−Ku) MAL is preferably comprised of hcp-CoIr while CoPt and FePt are examples of a (+Ku) MAL. The MAL has a down-track thickness from 5 to 20 nm, a width equal to the track width in a cross-track direction, and extends 100 to 500 nm in a direction toward a back end of the main pole. As a result, flux leakage from the main pole to trailing shield is reduced and aerial density is increased. A method for fabricating the PMR writer is provided. | 10-11-2012 |
20120295132 | Writer design with enhanced writability - A perpendicular magnetic recording (PMR) head is fabricated with a main pole and a trailing edge shield having surfaces and interior portions that may include synthetic antiferromagnetic multi-layered superlattices (SAFS) formed on and/or within them respectively. The SAFS, which are multilayers formed as periodic multiples of antiferromagnetically coupled tri-layers, provide a mechanism for enhancing the component of the writing field that is vertical to the magnetic medium by exchange coupling to the magnetization of the pole and shield and constraining the directions of their magnetizations to lie within the film plane of the SAFS. | 11-22-2012 |
20120295133 | Writer with an AFM write gap - A perpendicular magnetic recording (PMR) head is fabricated with main pole and a trailing edge shield antiferromagnetically coupled across a write gap by either having the write gap layer formed as a synthetic antiferromagnetic tri-layer (SAF) or formed as a monolithic layer of antiferromagnetic material. The coupling improves the write performance of the writer by enhancing the perpendicular component of the write field and its gradient. Methods of fabricating the writer are provided. | 11-22-2012 |
20120314324 | Non-uniform write gap perpendicular writer for shingle writing - A PMR writer is disclosed that includes at least one of a recessed center section in the write pole trailing edge and a center recessed trailing shield to improve the field gradient at track edge. In all embodiments, there is a non-uniform write gap between the trailing edge and the trailing shield. The recessed portion of the write pole trailing edge and/or center recess of the trailing shield has a thickness from 10 to 40 nm in a down-track direction and a width in a cross-track direction of 20 to 200 nm. The distance between the center recess and a corner of the trailing edge is from 20 to 80 nm. A sequence of steps is provided to fabricate the two embodiments of the present invention. | 12-13-2012 |
20130027809 | HIGH DATA RATE MAGNETIC WRITER DESIGN - A high speed magnetic data writer containing a stitched pole tip that works in conjunction with the main pole is disclosed, together with a process for their manufacture. The material composition of each of these two sub-structures is slightly different; one sub-structure is optimized for high magnetic damping while the other sub-structure is optimized for high saturation magnetization. | 01-31-2013 |
20140078619 | Shield Designs with Internal Magnetization Control for ATE Improvement - A magnetic recording head is fabricated with a pole tip shielded laterally on its sides by a pair of symmetrically disposed side shields formed of porous heterogeneous material that contains non-magnetic inclusions. The non-magnetic inclusions, when properly incorporated within the magnetic matrix of the shields, promote the formation of flux loops within the shields that have portions that are parallel to the ABS and do not display locally disorganized and dynamic regions of flux during the creation of magnetic transitions within the recording medium by the magnetic pole. These flux loop portions, combine with the magnetic flux emerging from the main pole to create a net writing field that significantly reduces adjacent track erasures (ATE) and wide area erasures (WATE). | 03-20-2014 |
20150055252 | Non-Uniform Write Gap Perpendicular Writer for Shingle Writing - A PMR writer is disclosed that includes a recessed center section in the write pole trailing edge and a center recessed trailing shield to improve the field gradient at track edge. In all embodiments, there is a non-uniform write gap between the trailing edge and the trailing shield. The recessed portion of the write pole trailing edge and/or center recess of the trailing shield has a thickness from 10 to 40 nm in a down-track direction and a width in a cross-track direction of 20 to 200 nm. The distance between the center recess and a corner of the trailing edge is from 20 to 80 nm. A sequence of steps is provided to fabricate the two embodiments of the present invention. | 02-26-2015 |
Patent application number | Description | Published |
20100314682 | Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions - This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches. | 12-16-2010 |
20110101446 | STAGGERED COLUMN SUPERJUNCTION - A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer. | 05-05-2011 |
20110127586 | Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode - A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate. | 06-02-2011 |
20110127606 | Lateral super junction device with high substrate-drain breakdwon and built-in avalanche clamp diode - This invention discloses configurations and methods to manufacture lateral power device including a super junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance. | 06-02-2011 |
20110147830 | METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS - Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns. | 06-23-2011 |
20110204442 | CORNER LAYOUT FOR SUPERJUNCTION DEVICE - A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions. | 08-25-2011 |
20120025261 | Method of minimizing field stop insulated gate bipolar transistor (IGBT) buffer and emitter charge variation - This invention discloses an insulated gate bipolar transistor (IGBT) formed in a semiconductor substrate. The IGBT comprises a buffer layer of a first conductivity type formed below an epitaxial layer of the first conductivity having body and source regions therein. The IGBT further includes a lowly doped substrate layer below the buffer layer and a dopant layer of a second conductivity type disposed below the lowly doped substrate layer and above a drain electrode of said IGBT attached to a bottom surface of said semiconductor substrate wherein the dopant layer of the second conductivity type has a higher dopant concentration than the lowly doped substrate layer. | 02-02-2012 |
20120193676 | Diode structures with controlled injection efficiency for fast switching - This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer. | 08-02-2012 |
20120248566 | Configuration and method to generate saddle junction electric field in edge termination - This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination. | 10-04-2012 |
20130277740 | CORNER LAYOUT FOR SUPERJUNCTION DEVICE - A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions. | 10-24-2013 |
20130341689 | METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS - Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate Source and body regions are formed by implanting dopants onto the filled trenches. This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns. | 12-26-2013 |
20150115333 | LATERAL SUPER JUNCTIONS WITH HIGH SUBSTRATE BREAKDOWN AND BUILD IN AVALANCHE CLAMP DIODE - This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance. | 04-30-2015 |
20150372129 | HIGH VOLTAGE FIELD BALANCE METAL OXIDE FIELD EFFECT TRANSISTOR (FBM) - A semiconductor device includes a semiconductor substrate of a first conductivity type. A first conductivity type epitaxial layer disposed on a top surface of the substrate includes a surface shielded region above a less heavily doped voltage blocking region. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the surface shielded region. A first conductivity type source region is disposed near the top surface inside the body region. A drain is disposed at a bottom surface of the substrate. A gate overlaps portions of the source and body regions. Gate insulation separates the gate from the source and body regions. First and second trenches formed in the surface shielded region are lined with trench insulation material and filled with electrically conductive trench filling material. Second conductivity type buried doped regions are positioned below the first and second trenches, respectively. | 12-24-2015 |
20160005809 | CONFIGURATION AND METHOD TO GENERATE SADDLE JUNCTION ELECTRIC FIELD IN EDGE TERMINATION - This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination. | 01-07-2016 |
Patent application number | Description | Published |
20100163846 | Nano-tube mosfet technology and devices - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches. | 07-01-2010 |
20100244090 | TVS with low capacitance & Forward voltage drop with depleted SCR as steering diode - A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage. | 09-30-2010 |
20100276779 | Transient Voltage Suppressor Having Symmetrical Breakdown Voltages - A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS. | 11-04-2010 |
20110049564 | Integrated schottky diode in high voltage semiconductor device - This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions. | 03-03-2011 |
20110073906 | High voltage MOSFET diode reverse recovery by minimizing P-body charges - This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions; and f) etching contact trenches into the source, body contact, and body regions. | 03-31-2011 |
20110183499 | Nano-tube MOSFET technology and devices - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches. | 07-28-2011 |
20120329238 | Method For Forming A Transient Voltage Suppressor Having Symmetrical Breakdown Voltages - A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS. | 12-27-2012 |
20130221430 | NANO-TUBE MOSFET TECHNOLOGY AND DEVICES - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches. | 08-29-2013 |
20140138737 | HIGH VOLTAGE MOSFET DIODE REVERSE RECOVERY BY MINIMIZING P-BODY CHARGES - This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions; and f) etching contact trenches into the source, body contact, and body regions. | 05-22-2014 |
20140167101 | TVS WITH LOW CAPACITANCE & FORWARD VOLTAGE DROP WITH DEPLETED SCR AS STEERING DIODE - A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage. | 06-19-2014 |
20160043169 | INTEGRATED SCHOTTKY DIODE IN HIGH VOLTAGE SEMICONDUCTOR DEVICE - This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions. | 02-11-2016 |
Patent application number | Description | Published |
20120319132 | SPLIT-GATE STRUCTURE IN TRENCH-BASED SILICON CARBIDE POWER DEVICE - An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region. | 12-20-2012 |
20130001694 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE - A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer. | 01-03-2013 |
20130001695 | UNI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) - An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region. | 01-03-2013 |
20130049102 | Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path - This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path. | 02-28-2013 |
20130075855 | Manufacturing methods for accurately aligned and self-balanced superjunction devices - A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers. | 03-28-2013 |
20130260522 | STAGGERED COLUMN SUPERJUNCTION - A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer. | 10-03-2013 |
20140027819 | CORNER LAYOUT FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES - A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform distance from the nearest termination device structure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 01-30-2014 |
20140027840 | TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE - The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 01-30-2014 |
20140027841 | HIGH VOLTAGE FIELD BALANCE METAL OXIDE FIELD EFFECT TRANSISTOR (FBM) - A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 01-30-2014 |
20140134825 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE - A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer. | 05-15-2014 |
20140193958 | TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE - The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 07-10-2014 |
20140231963 | UNI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) - A unidirectional transient voltage suppressor (TVS) device includes first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter. | 08-21-2014 |
20140319604 | HIGH VOLTAGE FIELD BALANCE METAL OXIDE FIELD EFFECT TRANSISTOR (FBM) - A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 10-30-2014 |
20140332919 | TERMINATION DESIGN FOR NANOTUBE MOSFET - A termination structure for a semiconductor power device includes a plurality of termination groups formed in a lightly doped epitaxial layer of a first conductivity type over a heavily doped semiconductor substrate of a second conductivity type. Each termination group includes a trench formed in the lightly doped epitaxial layer of the first conductivity type. All sidewalls of the trench are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two opposite sides and substantially symmetrical with respect to a central gap-filler layer disposed between two innermost epitaxial layers of an innermost conductivity type as the first conductivity type. | 11-13-2014 |
20140363946 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE - A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer. | 12-11-2014 |
20150108568 | SEMICONDUCTOR STRUCTURE WITH HIGH ENERGY DOPANT IMPLANTATION - A semiconductor device has an epitaxial layer grown over a substrate, each having a first dopant type. A structure disposed within the epitaxial layer has multiple trenches, each of which has a gate and a source electrode disposed within a shield oxide matrix. Multiple mesas each isolate a pair of the trenches from each other. A body region with a second dopant type is disposed above the epitaxial layer and bridges each of the mesas. A region of elevated concentration of the first dopant type is implanted at a high energy level between the epitaxial layer and the body region, which reduces resistance spreading into a channel of the device. A source region having the first dopant type is disposed above the body region. | 04-23-2015 |
20150118810 | BURIED FIELD RING FIELD EFFECT TRANSISTOR (BUF-FET) INTEGRATED WITH CELLS IMPLANTED WITH HOLE SUPPLY PATH - This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. Source trenches are opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. A buried field ring regions is disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, there are doped regions doped with a dopant of a same conductivity type of the buried field ring regions surrounding the sidewalls of the source trenches to function as a charge supply path. | 04-30-2015 |
20150279984 | TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE - The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 10-01-2015 |
20150311295 | SPLIT POLY CONNECTION VIA THROUGH-POLY-CONTACT (TPC) IN SPLIT-GATE BASED POWER MOSFETS - Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 10-29-2015 |
20150349101 | INJECTION CONTROL IN SEMICONDUCTOR POWER DEVICES - Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first buffer layer. An epitaxial layer of the second conductivity type formed above the second buffer layer. A doping concentration of the epitaxial layer is greater than a doping concentration of the second buffer layer. This abstract is provided to allow a searcher or reader to quickly ascertain the subject matter of the disclosure with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 12-03-2015 |
20150357406 | MANUFACTURING METHODS FOR ACCURATELY ALIGNED AND SELF-BALANCED SUPERJUNCTION DEVICES - This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers. | 12-10-2015 |
20160087095 | SEMICONDUCTOR DEVICE INCLUDING SUPERJUNCTION STRUCTURE FORMED USING ANGLED IMPLANT PROCESS - A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device. | 03-24-2016 |
20160118459 | CORNER LAYOUT FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES - A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform distance from the nearest termination device structure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 04-28-2016 |
Patent application number | Description | Published |
20100166422 | Isolation Switch for Fibre Channel Fabrics in Storage Area Networks - An isolation switch blade Fibre Channel switch presents F_ports to form a first Fibre Channel fabric and N_ports to a second Fibre Channel fabric to appear as node devices. The isolation switch blade may be used to connect a plurality of blade servers to a Fibre Channel fabric. Fabric events engendered by the insertion or removal of hot-pluggable devices are handled by the isolation switch blade and “event storms” on the Fibre Channel fabric are avoided. The isolation switch blade presents the blade servers to the FC fabric as a virtualized N_port. | 07-01-2010 |
20110196986 | Isolation Switch for Fibre Channel Fabrics in Storage Area Networks - An isolation switch blade Fibre Channel switch presents F_ports to form a first Fibre Channel fabric and N_ports to a second Fibre Channel fabric to appear as node devices. The isolation switch blade may be used to connect a plurality of blade servers to a Fibre Channel fabric. Fabric events engendered by the insertion or removal of hot-pluggable devices are handled by the isolation switch blade and “event storms” on the Fibre Channel fabric are avoided. The isolation switch blade presents the blade servers to the FC fabric as a virtualized N_port. | 08-11-2011 |
20120011297 | Isolation Switch for Fibre Channel Fabrics in Storage Area Networks - An isolation switch blade Fibre Channel switch presents F_ports to form a first Fibre Channel fabric and N_ports to a second Fibre Channel fabric to appear as node devices. The isolation switch blade may be used to connect a plurality of blade servers to a Fibre Channel fabric. Fabric events engendered by the insertion or removal of hot-pluggable devices are handled by the isolation switch blade and “event storms” on the Fibre Channel fabric are avoided. The isolation switch blade presents the blade servers to the FC fabric as a virtualized N_port. | 01-12-2012 |
20120044933 | METHOD AND APPARATUS FOR ROUTING BETWEEN FIBRE CHANNEL FABRICS - An interfabric link between two separate Fibre Channel fabrics so that devices in one fabric can communicate with devices in another fabric without requiring the merger of the two fabrics. The interfabric switch performs a conversion or a translation of device addresses in each fabric so that they are accessible to the other fabric. In a first embodiment the external ports of the interfabric switch are configured as E_ports. A series of internal ports in each interfabric switch are joined together forming a series of virtual or logical switches. In a second embodiment the external ports are configured as NL_ports and the connections between the virtual switches are E_ports. The virtual switches in the interfabric switch match domains with their external counterparts so that the virtual switches effectively form their own fabric. | 02-23-2012 |
20120044934 | METHOD AND APPARATUS FOR ROUTING BETWEEN FIBRE CHANNEL FABRICS - An interfabric link between two separate Fibre Channel fabrics so that devices in one fabric can communicate with devices in another fabric without requiring the merger of the two fabrics. The interfabric switch performs a conversion or a translation of device addresses in each fabric so that they are accessible to the other fabric. In a first embodiment the external ports of the interfabric switch are configured as E_ports. A series of internal ports in each interfabric switch are joined together forming a series of virtual or logical switches. In a second embodiment the external ports are configured as NL_ports and the connections between the virtual switches are E_ports. The virtual switches in the interfabric switch match domains with their external counterparts so that the virtual switches effectively form their own fabric. | 02-23-2012 |
20160006674 | METHOD AND APPARATUS FOR ROUTING BETWEEN FIBRE CHANNEL FABRICS - An interfabric link between two separate Fibre Channel fabrics so that devices in one fabric can communicate with devices in another fabric without requiring the merger of the two fabrics. The interfabric switch performs a conversion or a translation of device addresses in each fabric so that they are accessible to the other fabric. This translation is preferably done using a private to public loop address translation. In a first embodiment the external ports of the interfabric switch are configured as E_ports. A series of internal ports in each interfabric switch are joined together forming a series of virtual or logical switches. The virtual switches are then interconnected using private loops. The use of the private loop is enabled by the presence of translation logic which converts fabric addresses to loop addresses and back so that loop and fabric devices can communicate. Because each port can do this translation and the private loop addressing does not include domain or area information, the change in addresses between the fabrics is simplified. In a second embodiment the external ports are configured as NL_ports and the connections between the virtual switches are E_ports. Thus the private to public and public to private translations are done at the external ports rather than the internal ports as in the prior embodiment. The virtual switches in the interfabric switch match domains with their external counterparts so that the virtual switches effectively form their own fabric, connected to the other fabrics by the private loops. | 01-07-2016 |
Patent application number | Description | Published |
20130003053 | DETERMINATION OF ABSOLUTE DIMENSIONS OF PARTICLES USED AS CALIBRATION STANDARDS FOR OPTICAL MEASUREMENT SYSTEM - The present invention includes providing a plurality of standard particles; providing a substantially crystalline material having one or more characteristic spatial parameters, disposing the plurality of standard particles proximate to a portion of the substantially crystalline material, acquiring imagery data of the plurality of standard particles and the portion of the substantially crystalline material, establishing a spatial relationship between the plurality of standard particles and the portion of the substantially crystalline material utilizing the acquired imagery data, and determining one or more spatial parameters of the plurality of standard particles utilizing the one or more characteristic spatial parameters of the substantially crystalline material and the established spatial relationship between the plurality of standard particles and the portion of the substantially crystalline material. | 01-03-2013 |
20140308456 | APPARATUS AND METHOD FOR CONTROLLED DEPOSITION OF AEROSOLIZED PARTICLES ONTO A SUBSTRATE - An apparatus for the controlled deposition of particles onto a film or a substrate, including: a frame arranged to support a film or a substrate having first and second surfaces facing in first and second opposite directions, respectively; a nozzle arranged to emit a stream of particles charged with a first polarity toward the first surface; and an electrode: charged with a second polarity, opposite the first polarity, and located adjacent the second surface; and arranged to attract the stream of particles to a region of the first surface. A line orthogonal to the first surface passes through the region and the electrode. | 10-16-2014 |
20150316411 | Method and System for Intrinsic LED Heating for Measurement - The present disclosure provides methods and apparatus for testing light-emitting diodes (LEDs), for example, measuring the optical radiation of an LED. In a method, a pulse-width modulated signal is provided to the LED. One or more characteristics of the PWM signal are varied so as to provide a forward voltage, V | 11-05-2015 |
20150316604 | LIGHT-EMITTING DEVICE TEST SYSTEMS - Light-emitting devices, such as LEDs, are tested using a photometric unit. The photometric unit, which may be an integrating sphere, can measure flux, color, or other properties of the devices. The photometric unit may have a single port or both an inlet and outlet. Light loss through the port, inlet, or outlet can be reduced or calibrated for. These testing systems can provide increased reliability, improved throughput, and/or improved measurement accuracy. | 11-05-2015 |
Patent application number | Description | Published |
20110261721 | METHOD AND SYSTEM ARCHITECTURE FOR A SELF ORGANIZING NETWORK - A method and system architecture for a self-organizing network (SON) includes a first cell having a first user equipment classifier for determining one of cell edge and cell central. The SON also includes a second cell having a second user equipment classifier for determining one of cell edge and cell central. The system architecture and method provide a first transmit time interval (TTI) schema for user equipment within the area of coverage associated with the first cell and a TTI schema for user equipment within the area of coverage associated with the second cell, the second TTI schema differing from the first TTI schema. The user equipment is classified as cell centre or cell edge in dependence upon at least one of QoS requirement, geometry, periodic PSMM and CQI reports. The TTI schemas are used for “cell edge” user equipment by the respective cells. | 10-27-2011 |
20140355481 | PROTOCOLS, INTERFACES, AND PRE/POST-PROCESSING FOR ENABLING SON ENTITIES AND FEATURES IN BASE STATIONS AND WIRELESS NETWORKS - LTE and HSPA/UMTS deployments are trending towards high density, heterogeneous and ad-hoc deployments. These deployments can be managed through Self-Organizing Network (SON) schemas. Enabling SON generally involves the introduction of new software and/or hardware entities into the network that can interact with existing base station and network entities (e.g., Enhanced Packet Core, Element Management System, and/or other network entities). In one embodiment, these interactions include the development and deployment of interfaces (e.g., APIs) and protocols between the SON entities and various network entities. For example, data collected on either side of an interface or protocol can be post-processed before consumption (e.g., for both data integrity purposes as well as bandwidth reduction purposes). As described herein, a full set of such interfaces and protocols with specific examples are disclosed to illustrate various techniques for providing protocols, interfaces, and pre/post-processing for enabling SON entities and features in base stations and wireless networks. | 12-04-2014 |
20150223287 | SELF-ORGANIZATION NETWORK ARCHITECTURES FOR HETEROGENEOUS NETWORKS - Self-Organized Network (SON) architectures for heterogeneous networks are disclosed. In some embodiments, various SON architectures for heterogeneous networks are provided that can evolve with such networks while the core functional modules of the SON solution can remain the same. In some embodiments, techniques for implementing SON architectures for heterogeneous networks includes providing a base station that includes performing a pre-operation self-configuration; and performing an operation self-optimization. | 08-06-2015 |
20160007369 | METHOD AND SYSTEM ARCHITECTURE FOR A SELF ORGANIZING NETWORK - A method and system architecture for a self-organizing network (SON) includes a first cell having a first user equipment classifier for determining one of cell edge and cell central. The SON also includes a second cell having a second user equipment classifier for determining one of cell edge and cell central. The system architecture and method provide a first transmit time interval (TTI) schema for user equipment within the area of coverage associated with the first cell and a TTI schema for user equipment within the area of coverage associated with the second cell, the second TTI schema differing from the first TTI schema. The user equipment is classified as cell centre or cell edge in dependence upon at least one of QoS requirement, geometry, periodic PSMM and CQI reports. The TTI schemas are used for “cell edge” user equipment by the respective cells. | 01-07-2016 |
Patent application number | Description | Published |
20080306229 | Transition Metal-Catalyzed Synthesis of Dendritic Polymers - Dendritic amphiphilic polymers are contemplated. Most preferably, such polymers will be fabricated in a single step to the final product that may further be derivatized with, among others, biological relevant molecules. In alternative aspects, precursors of such molecules are prepared in a single step, and the precursors are then reacted to the dendritic amphiphilic polymers. | 12-11-2008 |
20080317861 | Polymeric Materials and Methods - Chimeric polymer compositions and methods are provided in which a plurality of carbohydrate moieties and amino acids form the backbone of a polymer. Most preferably, the polymer includes alternating saccharide and peptide portions to form the chimeric polymer. | 12-25-2008 |
20140045997 | OLEFIN METATHESIS FOR EFFECTIVE POLYMER HEALING VIA DYNAMIC EXCHANGE OF STRONG CARBON-CARBON BONDS - A method of preparing a malleable and/or self-healing polymeric or composite material is provided. The method includes providing a polymeric or composite material comprising at least one alkene-containing polymer, combining the polymer with at least one homogeneous or heterogeneous transition metal olefin metathesis catalyst to form a polymeric or composite material, and performing an olefin metathesis reaction on the polymer so as to form reversible carbon-carbon double bonds in the polymer. Also provided is a method of healing a fractured surface of a polymeric material. The method includes bringing a fractured surface of a first polymeric material into contact with a second polymeric material, and performing an olefin metathesis reaction in the presence of a transition metal olefin metathesis catalyst such that the first polymeric material forms reversible carbon-carbon double bonds with the second polymeric material. Compositions comprising malleable and/or self-healing polymeric or composite material are also provided. | 02-13-2014 |
20140242123 | SACCHARIDE-PEPTIDE HYDROGELS - The disclosure provides for saccharide-peptide based hydrogels, the functionalization of the saccharide-peptide based hydrogels with one or more biological agents, and the encapsulation of one or more biological materials and/or pharmaceutical agents in the hydrogels. The disclosure further provides for the use of the saccharide-peptide based hydrogels in treating a disease or disorder in a subject. | 08-28-2014 |
20140288150 | DENDRONIZED POLYMERS FOR NUCLEIC ACID DELIVERY - The disclosure provides for dendronized polymers, and the use of the polymers as carriers for the intracellular delivery of nucleic acids. | 09-25-2014 |
20150038649 | BIO-INSPIRED METHOD OF OBTAIN MULTIFUNCTIONAL DYNAMIC NANOCOMPOSITES - A method for a polymeric or nanocomposite material. The method includes assembling a multiphase hard-soft structure, where the structure includes a hard micro- or nano-phase, and a soft micro- or nano-phase that includes a polymeric scaffold. In the method, the polymeric scaffold includes dynamically interacting motifs and has a glass transition temperature (T | 02-05-2015 |
20160030590 | VECTORS FOR DELIVERY OF AGENTS ACROSS BIOLOGICAL MEMBRANES - The disclosure provides for peptide-based bolaamphiphile vectors that are capable of encapsulating a variety of agents, including peptides, proteins, nucleic acids, and drugs. The disclosure further provides for delivering these agents across biological membranes using the peptide-based bolaamphiphile vectors. | 02-04-2016 |