Patent application number | Description | Published |
20090300440 | DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE - A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences. | 12-03-2009 |
20090300441 | ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE - A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode. | 12-03-2009 |
20090307543 | TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE - An apparatus comprising a controller, a plurality of transport circuits and a plurality of memory-controlling circuits. The controller may be configured to (i) present one or more commands and (ii) receive one or more responses. Each of the plurality of transport circuits may be configured to (i) receive one of the commands, (ii) present the responses, and (iii) generate one or more control signals. Each of the plurality of memory-controlling circuits may be (i) coupled to a respective one of the plurality of transport circuits and (ii) configured to (i) generate one or more memory access signals in response to the one or more control signals, (ii) receive one or more memory output signals from a respective memory in response to the one or more memory access signals and (iii) generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits. | 12-10-2009 |
20100057823 | Alternate galois field advanced encryption standard round - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round. | 03-04-2010 |
20100086127 | EFFICIENT IMPLEMENTATION OF ARITHMETICAL SECURE HASH TECHNIQUES - An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog. | 04-08-2010 |
20100293421 | LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS - An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals. | 11-18-2010 |
20110029980 | LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS - An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals. | 02-03-2011 |
20110320397 | IMPULSE REGULAR EXPRESSION MATCHING - Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied. | 12-29-2011 |
20120121079 | CIPHER INDEPENDENT INTERFACE FOR CRYPTOGRAPHIC HARDWARE SERVICE - Disclosed is a cipher independent cryptographic hardware service. Cipher independent transactions are received into input slots ( | 05-17-2012 |
20130024668 | ARCHITECTURE AND IMPLEMENTATION METHOD OF PROGRAMMABLE ARITHMETIC CONTROLLER FOR CRYPTOGRAPHIC APPLICATIONS - An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography. | 01-24-2013 |
20140136465 | IMPULSE REGULAR EXPRESSION MATCHING - Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied. | 05-15-2014 |
Patent application number | Description | Published |
20080270505 | EFFICIENT HARDWARE IMPLEMENTATION OF TWEAKABLE BLOCK CIPHER - A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T | 10-30-2008 |
20090100390 | Low Depth Circuit Design - A method of designing a logic circuit based on one of the functions of the form f | 04-16-2009 |
20100017622 | High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks - The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device. | 01-21-2010 |
20100191935 | Architecture and implementation method of programmable arithmetic controller for cryptographic applications - An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography. | 07-29-2010 |
20110255689 | MULTIPLE-MODE CRYPTOGRAPHIC MODULE USABLE WITH MEMORY CONTROLLERS - In one embodiment, a multi-mode Advanced Encryption Standard (MM-AES) module for a storage controller is adapted to perform interleaved processing of multiple data streams, i.e., concurrently encrypt and/or decrypt string-data blocks from multiple data streams using, for each data stream, a corresponding cipher mode that is any one of a plurality of AES cipher modes. The MM-AES module receives a string-data block with (a) a corresponding key identifier that identifies the corresponding module-cached key and (b) a corresponding control command that indicates to the MM-AES module what AES-mode-related processing steps to perform on the data block. The MM-AES module generates, updates, and caches masks to preserve inter-block information and allow the interleaved processing. The MM-AES module uses an unrolled and pipelined architecture where each processed data block moves through its processing pipeline in step with correspondingly moving key, auxiliary data, and instructions in parallel pipelines. | 10-20-2011 |
20120076298 | UNIFIED ARCHITECTURE FOR CRYPTO FUNCTIONAL UNITS - In described embodiments, a unified Crypto Functional Unit (CFU) block architecture provides a capability for advanced communication processors to provide parallel and concurrent processing of multiple crypto operations/transactions within high-speed hardware to support different security standards (e.g. from IPsec, 3GPP). In particular, each CFU block of the unified CFU block architecture comprises a FIFO-based interface, switch, and wrapped cipher/hasher. The unified CFU block architecture allows for drop-in solutions for cipher blocks in ASIC designs with crypto function blocks. | 03-29-2012 |
20120159407 | Low Depth Circuit Design - A method of designing a logic circuit based on one of the functions of the form f | 06-21-2012 |
20120226731 | LOW DEPTH COMBINATIONAL FINITE FIELD MULTIPLIER - A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field. | 09-06-2012 |
20120324319 | HIGH THROUGHPUT FRAME CHECK SEQUENCE MODULE ARCHITECTURE - Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products. | 12-20-2012 |
20130283114 | Systems and Methods for Locating and Correcting Decoder Mis-Corrections - Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit. | 10-24-2013 |
20140075264 | CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING - A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword. | 03-13-2014 |
20140164866 | Low Density Parity Check Decoder With Miscorrection Handling - A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected. | 06-12-2014 |
20140168811 | Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling - A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome. | 06-19-2014 |
20140281284 | MULTI-READ PORT MEMORY - A method includes receiving a multi-port read request for retrieval of data stored in three memories, each comprising two memory modules and a parity module. The multi-port read request is associated with first data stored at a first memory address, second data stored at a second memory address, and third data stored at a third memory address. When the first memory address, the second memory address, and the third memory address are associated with a first memory module, first data is retrieved from the first memory module, second data is reconstructed using data from a second memory module and a first parity module, and third data is reconstructed using data from a fourth memory module and a seventh memory module. The first data, the second data, and the third data are provided in response to the multi-port read request. | 09-18-2014 |
20140325303 | Systems and Methods for Protected Data Encoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for encoding data sets. | 10-30-2014 |