Patent application number | Description | Published |
20090040081 | ENCODING AND DECODING METHODS USING GENERALIZED CONCATENATED CODES (GCC) - Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level. | 02-12-2009 |
20090055717 | ARCHITECTURE AND CONTROL OF REED-SOLOMON LIST DECODING - Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes. | 02-26-2009 |
20090063937 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-05-2009 |
20090083608 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-26-2009 |
20090150746 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the | 06-11-2009 |
20090292976 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR IDENTIFICATION AND EVALUATION - Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials. | 11-26-2009 |
20100269026 | ERROR PATTERN GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING - The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths. | 10-21-2010 |
20110043390 | ENCODING AND DECODING METHODS USING GENERALIZED CONCATENATED CODES (GCC) - Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level. | 02-24-2011 |
20110055664 | SYSTEMS AND METHODS FOR COMPRESSING DATA IN NON-VOLATILE SEMICONDUCTOR MEMORY DRIVES - A non-volatile semiconductor memory (NVSM) storage system includes a NVSM drive interface configured to receive host data sectors (HDSs) from a host interface. A buffer managing module is configured to store the HDSs in a buffer. A compression module is configured to compress the HDSs to generate compressed HDSs of different lengths. A drive data sector (DDS) generating module is configured to add nuisance data to the compressed HDSs to generate DDSs. The DDSs are stored in NVSM. | 03-03-2011 |
20110066793 | Implementing RAID In Solid State Memory - The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving data to be stored, dividing data into logical data blocks, assigning the blocks to a logical block grouping comprising at least one physical data storage block from two or more of multiple solid state physical memory devices, storing the blocks in physical data storage blocks, determining a code that corresponds to the persisted data, and storing the code that corresponds to the data stored in the logical block grouping. Blocks of damaged stored data may be recovered by identifying the logical data block and logical block grouping corresponding to the damaged physical data storage block, reading the data and the code stored in the identified grouping, and comparing the code to the read data other than the data stored in the damaged block. | 03-17-2011 |
20110087933 | POWER CONSUMPTION IN LDPC DECODER FOR LOW-POWER APPLICATIONS - This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders. | 04-14-2011 |
20110202711 | ADAPTIVE READ AND WRITE SYSTEMS AND METHODS FOR MEMORY CELLS - An apparatus including: a plurality of multi-level memory cells configured to store data, wherein one or more of the multi-level memory cells are designated as pilot memory cells, and wherein each pilot memory cell is configured to store known, pre-determined data; an estimation block configured to, based on the known, pre-determined data, determine (i) estimated mean values of level distributions of the multi-level memory cells and (ii) estimated standard deviation values of level distributions of the multi-level memory cells; and a computation block configured to compute at least optimal or near optimal detection threshold values of level distributions of the multi-level memory cells based, at least in part, on (i) the estimated mean values and (ii) the estimated standard deviation values, wherein the optimal or near optimal detection threshold values are to be used in order to facilitate reading of the data stored in the multi-level memory cells. | 08-18-2011 |
20110225477 | SYSTEMS AND METHODS FOR ACHIEVING HIGHER CODING RATE USING PARITY INTERLEAVING - The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information. | 09-15-2011 |
20120137197 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 05-31-2012 |
20120185744 | LDPC MULTI-DECODER ARCHITECTURES - Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix that corresponds to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check matrix is coupled to a high throughput LDPC decoder and a low throughput LDPC decoder, The super-parity-check matrix includes n parity check matrices, each including x rows corresponding to x check node processing elements and y columns corresponding to y bit node processing elements. Thus, the super-parity-check matrix comprises nx rows and ny columns. The numbers n, x, and y are selected so that ny codeword can be processed in single time unit by the high throughput decoder and y codeword bits can be processed in a single time unit by the low throughput decoder. | 07-19-2012 |
20120198135 | Mapping Data to Non-Volatile Memory - The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance. | 08-02-2012 |
20120198314 | SOFT DECODING SYSTEMS AND METHODS FOR FLASH BASED MEMORY SYSTEMS - Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword. | 08-02-2012 |
20120233524 | LOW-DENSITY PARITY CHECK CODES FOR HOLOGRAPHIC STORAGE - Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput. | 09-13-2012 |
20120278686 | SYSTEMS AND METHODS FOR ACHIEVING HIGHER CODING RATE USING PARITY INTERLEAVING - The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information. | 11-01-2012 |
20120284588 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 11-08-2012 |
20120300545 | SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH - Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices. | 11-29-2012 |
20120317460 | IDENTIFICATION AND MITIGATION OF HARD ERRORS IN MEMORY SYSTEMS - Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation. | 12-13-2012 |
20130073922 | METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF ITERATIVE DECODERS ON CHANNELS WITH MEMORY - Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode. | 03-21-2013 |
20130155776 | INTER-CELL INTERFERENCE CANCELLATION - A method includes selecting a first memory cell located along a first bit line and a first word line of a memory array. The method further includes selecting a second memory cell located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. A location of the second memory cell is selected based on a predetermined sequence of programming the memory cells. The method further includes writing data in the first memory cell, subsequently writing data in the second memory cell, and reading the first memory cell and the second memory cell. The method further includes detecting one or more states of the second memory causing interference to the first memory cell. | 06-20-2013 |
20130219104 | METHOD AND APPARATUS FOR COMPRESSING DATA SECTORS IN STORAGE DRIVE - A storage drive includes a non-volatile semiconductor memory, and interface, a compression module, a sector module, and a control module. The interface is configured to receive first data sectors transmitted from a host to the storage drive. The compression module is configured to compress the first data sectors to generate second data sectors. Lengths of the second data sectors vary. The first sector module is configured to generate third data sectors by adding nuisance data to (i) the second data sectors, or (ii) an encrypted version of the second data sectors, wherein lengths of the third data sectors do not vary. The control module is configured to store the third data sectors in the non-volatile semiconductor memory. | 08-22-2013 |
20130232389 | POWER CONSUMPTION IN LDPC DECODER FOR LOW-POWER APPLICATIONS - This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders. | 09-05-2013 |
20130246879 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D | 09-19-2013 |
20140002918 | SYSTEMS AND METHODS FOR READING AND DECODING ENCODED DATA FROM A STORAGE DEVICE | 01-02-2014 |
20140143641 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D | 05-22-2014 |
20140160855 | SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH - Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices. | 06-12-2014 |
20140237287 | IMPLEMENTING RAID IN SOLID STATE MEMORY - The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a data request for a solid state memory; identifying a logical block grouping corresponding to the data request, wherein the logical block grouping indicates physical data storage blocks spanning at least two distinct memory units of the solid state memory; reading stored data and parity information from at least a portion of the physical data storage blocks spanning the at least two distinct memory units; and recovering data of at least one block of the logical block grouping based on the stored data and the parity information. | 08-21-2014 |
20140289584 | SYSTEMS AND METHODS FOR MULTI-STAGE SOFT INPUT DECODING - Systems and methods are provided for decoding data. A first decoder attempts to decode the data based on a hard decision input for a symbol. When the attempt to decode the data based on the hard decision input fails, a request is transmitted reliability information for the symbol. Receiving circuitry receives the reliability information for the symbol, and a second decoder decodes the data based on the reliability information. | 09-25-2014 |
20140298130 | LDPC MULTI-DECODER ARCHITECTURES - Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix corresponding to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check-matrix is configured to operate with nx check node processing elements (NPEs) and ny bit NPEs. The super-parity-check matrix includes a plurality of parity check matrices. Each parity check matrix is configured to operate with x check NPEs and y bit NPEs. The numbers n, x, and y, are selected such that ny codeword bits are processed in the single time unit by a high throughput decoder and y codeword bits are processed in the single time unit by a low throughput decoder. | 10-02-2014 |
20140344647 | NAND FLASH MEMORY SYSTEMS WITH EFFICIENT SOFT INFORMATION INTERFACE - A controller for a nonvolatile memory device includes a transfer control module and a decoder module. The transfer control module is configured to request a read of data from a flash memory module. The data to be read includes data corresponding to a first codeword. The transfer control module is configured to receive hard decisions corresponding to the first codeword from the flash memory module. The transfer control module is configured to receive soft information corresponding to the first codeword from the flash memory module. Both the hard decisions corresponding to the first codeword and the soft information corresponding to the first codeword are received without receiving any intervening hard decisions or soft information corresponding to another codeword. The decoder module is configured to decode the first codeword using the hard decisions and the soft information corresponding to the first codeword. | 11-20-2014 |
20140372687 | MAPPING DATA TO NON-VOLATILE MEMORY - An apparatus includes, in at least one aspect, a memory interface configured to connect with a plurality of multi-level memory cells and a circuitry coupled with the memory interface. The plurality of multi-level memory cells include a first page and a second page. The first page is associated with bits of a first significance. The second page is associated with bits of a second significance. The circuitry is configured to map a first portion of an encoded data sector to the first page and map a second portion of the encoded data sector to the second page. The first portion excludes the second portion and the second portion excludes the first portion such that each of the first page and the second page contains different data from the encoded data sector. | 12-18-2014 |
20150022916 | SYSTEMS AND METHODS FOR CALIBRATING READ AND WRITE OPERATIONS IN TWO DIMENSIONAL MAGNETIC RECORDING - Systems and methods are provided for calibrating signals retrieved from a storage device using a first reader and a second reader. The systems and methods further include reading a first signal using the first reader and a second signal using the second reader. Control circuitry computes a calibration metric associated with the first reader and the second reader based on the combination of the first signal and the second signal. At least one of the first signal and the second signal is subsequently decoded based in part on the computed calibration metric. | 01-22-2015 |