| Patent application number | Description | Published |
|---|
| 20100082912 | SYSTEMS AND METHODS FOR RESOURCE ACCESS - Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged. | 04-01-2010 |
| 20100153799 | METHOD AND APPARATUS FOR LOOPBACK SELF TESTING - A system and method for loopback self testing. A system includes a host device and an endpoint device. The host device transmits unencoded test symbols. The endpoint device loops back the unencoded test symbols to the host device. The host device drives at least some bits of each unencoded test symbol onto host device data signals and drives at least some bits of each unencoded test symbol onto host device control signals. | 06-17-2010 |
| 20110179423 | MANAGING LATENCIES IN A MULTIPROCESSOR INTERCONNECT - In a computing system having a plurality of transaction source nodes issuing transactions into a switching fabric, an underserviced node notifies source nodes in the system that it needs additional system bandwidth to timely complete an ongoing transaction. The notified nodes continue to process already started transactions to completion, but stop the introduction of new traffic into the fabric until such time as the underserviced node indicates that it has progressed to a preselected point. | 07-21-2011 |
| 20130188647 | COMPUTER SYSTEM FABRIC SWITCH HAVING A BLIND ROUTE - A fabric switch includes ports, a blind route determination function component, a location function component, and a routing function component. Packets are received and forwarded via the ports. The blind route determination function component determines whether a port at which a packet is received is configured for a blind route, the location function component provides for determining a location of routing information within the packet based at least in part on the input port at which the packet was received if a blind route is not defined for the port. The routing function component provides for determining an output port as a routing function based at least in part on the contents of the location, or the existence of a blind route. | 07-25-2013 |
| 20140324746 | TRAINING SEQUENCE - A computing system can include a memory controller and a first storage device. The first storage device is to receive a serially encoded request and forward the serially encoded request to a second storage device before deserializing the serially encoded request. The first storage device is also to return a training sequence from the target storage device to the memory controller. The first storage device is additionally to return a response from the target storage device to the memory controller. | 10-30-2014 |
| 20150039873 | PROCESSOR PROVIDING MULTIPLE SYSTEM IMAGES - An example processor includes a plurality of processing core components, one or more memory interface components, and a management component, wherein the one or more memory interface components are each shared by the plurality of processing core components, and wherein the management component is configured to assign each of the plurality of processing core components to one of a plurality of system images. | 02-05-2015 |
| 20150113245 | ADDRESS TRANSLATION GASKET - An example processor includes a plurality of processor core components, a memory interface component, and an address translation gasket. Each processor core component is assigned to one of a plurality of system images, and the plurality of system images share a common memory component by at least utilizing the address translation gasket to maintain separation between memory regions assigned to each of the plurality of system images. The memory interface component is shared by the plurality of independent system images. The address translation gasket is configured to intercept transactions bound for the memory interface component comprising a system image identifier and a target address, generate a translation address based at least in part on the system identifier and the target address, and send the translation address to the memory interface component. | 04-23-2015 |
| 20150378823 | MEMORY DEVICE HAVING ERROR CORRECTION LOGIC - Data is read from memory cells in the memory device. The read data is transferred over a link to a memory controller that is external of the memory device. While the transferring of the read data is ongoing, error detection of the read data is performed inside the memory device using an error correction code. | 12-31-2015 |
