Patent application number | Description | Published |
20090003233 | Method, Apparatus, and Computer Program Product for Identifying Selected Applications Utilizing a Single Existing Available Bit In Frame Headers - A method, apparatus, and computer program product are disclosed for collecting data about the transmission of network packets that are associated with specified applications. The packets are transmitted through a communications network fabric that is used to couple data processing systems together. A particular existing single bit in a frame header definition is selected. The bit is defined as part of the standard frame header by a communication protocol as an available bit in the frame header. The standard protocol is unchanged by the selection of this bit. An application is specified to be monitored. The selected bit is then set in each network packet that is generated by the specified application. The fabric collects performance data for each packet that has the bit set. Thus, the fabric collects performance data about a transmission of each packet that is generated by the application when that application is setting the bit. | 01-01-2009 |
20120072705 | Obtaining And Releasing Hardware Threads Without Hypervisor Involvement - A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly. | 03-22-2012 |
20120072707 | Scaleable Status Tracking Of Multiple Assist Hardware Threads - A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating. | 03-22-2012 |
20120210102 | Obtaining And Releasing Hardware Threads Without Hypervisor Involvement - A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly. | 08-16-2012 |
20120226946 | Assist Thread Analysis and Debug Mechanism - A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area. | 09-06-2012 |
20120284717 | Assist Thread Analysis and Debug Mechanism - A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area. | 11-08-2012 |
20130139168 | Scaleable Status Tracking Of Multiple Assist Hardware Threads - A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating. | 05-30-2013 |
20140282616 | BIDIRECTIONAL COUNTING OF DUAL OUTCOME EVENTS - A dual outcome event monitoring unit comprises a plurality of inputs, and a first counter. Each input is associated with an event and the first counter is a bidirectional counter. The dual outcome event monitoring unit is configured to increment the first counter in response to receiving an indication of the occurrence of a first event of a plurality of events. The first event is designated as an increment event. The dual outcome event monitoring unit is also configured to decrement the first counter responsive to receiving an indication of the occurrence of a second event of a plurality of events. The second event is designated as a decrement event. | 09-18-2014 |
20140282622 | BIDIRECTIONAL COUNTING OF DUAL OUTCOME EVENTS - An indication that an event occurred is received from a processor by a dual outcome event monitoring unit. It is determined whether the event is associated with an increment event or a decrement event. In response to determining that the event is associated with the increment event, an event counter is incremented. The event counter is part of the dual outcome monitoring unit. In response to determining that the event is associated with the decrement event, the event counter is decremented. | 09-18-2014 |