Patent application number | Description | Published |
20090072313 | HARDENED TRANSISTORS IN SOI DEVICES - A series transistor device includes a series source, a series drain, a first constituent transistor, and a second constituent transistor. The first constituent transistor has a first source and a first drain, and the second constituent transistor has a second source and a second drain. All of the constituent transistors have a same conductivity type. The series source is the first source, and the series drain is the second drain. A drain of one of the constituent transistors is merged with a source of another of the constituent transistors. | 03-19-2009 |
20100032684 | ION IMPLANTATION FOR SUPPRESSION OF DEFECTS IN ANNEALED SiGe LAYERS - A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided. | 02-11-2010 |
20100035409 | CRYSTALLINE SILICON SUBSTRATES WITH IMPROVED MINORITY CARRIER LIFETIME - A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl. | 02-11-2010 |
20110115023 | HYBRID FinFET/PLANAR SOI FETs - A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices. | 05-19-2011 |
20110117712 | SEMICONDUCTOR DEVICE WITH HIGH K DIELECTRIC CONTROL TERMINAL SPACER STRUCTURE - A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region. | 05-19-2011 |
20110254080 | TUNNEL FIELD EFFECT TRANSISTOR - A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack. | 10-20-2011 |
20110263104 | THIN BODY SEMICONDUCTOR DEVICES - A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented. | 10-27-2011 |
20110284967 | Stressed Fin-FET Devices with Low Contact Resistance - A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device. | 11-24-2011 |
20110303915 | Compressively Stressed FET Device Structures - Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins. | 12-15-2011 |
20110309333 | SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE - A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions. | 12-22-2011 |
20110309446 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 12-22-2011 |
20120009766 | STRAINED SEMICONDUCTOR-ON-INSULATOR BY ADDITION AND REMOVAL OF ATOMS IN A SEMICONDUCTOR-ON-INSULATOR - A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate. | 01-12-2012 |
20120012933 | FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE - A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space. | 01-19-2012 |
20120032267 | DEVICE AND METHOD FOR UNIFORM STI RECESS - A semiconductor device and method for forming the semiconductor device include forming structures in a semiconductor substrate. The structures have two or more different spacings between them. A dielectric material is deposited in the spacings. Ion species are implanted to a depth in the dielectric material to change an etch rate of the dielectric material down to the depth. The dielectric material having the ion species is etched selective to the dielectric material below the depth such that a substantially uniform depth in the dielectric material is created across the at least two spacings. | 02-09-2012 |
20120153397 | Stressed Fin-FET Devices with Low Contact Resistance - An FET device includes a plurality of Fin-FET devices. The fins of the Fin-FET devices are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device. | 06-21-2012 |
20120187493 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME - An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided. | 07-26-2012 |
20120205784 | GROWING COMPRESSIVELY STRAINED SILICON DIRECTLY ON SILICON AT LOW TEMPERATURES - Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient. | 08-16-2012 |
20120210932 | LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE INTEGRATION - An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000. | 08-23-2012 |
20120223292 | Multilayer-Interconnection First Integration Scheme for Graphene and Carbon Nanotube Transistor Based Integration - Integrated circuit multilayer integration techniques are provided. In one aspect, a method of fabricating an integrated circuit is provided. The method includes the following steps. A substrate is provided. A plurality of interconnect layers are formed on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack. At least one transistor is formed on a top-most layer of the stack. | 09-06-2012 |
20120235239 | HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined. | 09-20-2012 |
20120241902 | SELF-ALIGNED DUAL DEPTH ISOLATION AND METHOD OF FABRICATION - FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer. | 09-27-2012 |
20120256260 | DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE - Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks. | 10-11-2012 |
20120261757 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 10-18-2012 |
20120267722 | Compressively Stressed FET Device Structures - An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins. | 10-25-2012 |
20120276695 | Strained thin body CMOS with Si:C and SiGe stressor - A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement. | 11-01-2012 |
20120286329 | SOI FET with embedded stressor block - A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the insulating layer. The voids are epitaxially filled with a semiconductor material of a differing lattice constant than the one of the SOI layer, thus becoming a stressor block, and imparts a strain onto the FET device body. | 11-15-2012 |
20120286350 | TUNNEL FIELD EFFECT TRANSISTOR - An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side. | 11-15-2012 |
20120286364 | Integrated Circuit Diode - A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process. | 11-15-2012 |
20120292705 | SEMICONDUCTOR STRUCTURE HAVING UNDERLAPPED DEVICES - A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively. | 11-22-2012 |
20120299075 | SOI Trench Dram Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion. | 11-29-2012 |
20120302020 | SOI Trench Dram Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion. | 11-29-2012 |
20120312361 | EMITTER STRUCTURE AND FABRICATION METHOD FOR SILICON HETEROJUNCTION SOLAR CELL - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type, and growing a doped amorphous or nanocrystalline passivation layer of a second conductivity type that is opposite to the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 12-13-2012 |
20120313143 | HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT - A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction. | 12-13-2012 |
20120313168 | FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION - An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer. | 12-13-2012 |
20120318336 | CONTACT FOR SILICON HETEROJUNCTION SOLAR CELLS - A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion. | 12-20-2012 |
20120319232 | Self-Aligned Dual Depth Isolation and Method of Fabrication - FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer. | 12-20-2012 |
20120325304 | CONTACT FOR SILICON HETEROJUNCTION SOLAR CELLS - A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion. | 12-27-2012 |
20120326230 | SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE - A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions. | 12-27-2012 |
20130014811 | HETEROJUNCTION III-V SOLAR CELL PERFORMANCEAANM Bedell; Stephen W.AACI Wappingers FallsAAST NYAACO USAAGP Bedell; Stephen W. Wappingers Falls NY USAANM Hekmatshoartabari; BahmanAACI Mount KiscoAAST NYAACO USAAGP Hekmatshoartabari; Bahman Mount Kisco NY USAANM Sadana; Devendra K.AACI PleasantvilleAAST NYAACO USAAGP Sadana; Devendra K. Pleasantville NY USAANM Shahidi; Ghavam G.AACI Pound RidgeAAST NYAACO USAAGP Shahidi; Ghavam G. Pound Ridge NY USAANM Shahrjerdi; DavoodAACI OssiningAAST NYAACO USAAGP Shahrjerdi; Davood Ossining NY US | 01-17-2013 |
20130025655 | HETEROJUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate. | 01-31-2013 |
20130025658 | HETEROJUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate. | 01-31-2013 |
20130093039 | HIGH-K DIELECTRIC AND SILICON NITRIDE BOX REGION - Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer. | 04-18-2013 |
20130099318 | THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate. | 04-25-2013 |
20130099319 | THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate. | 04-25-2013 |
20130112275 | SILICON HETEROJUNCTION PHOTOVOLTAIC DEVICE WITH WIDE BAND GAP EMITTER - A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm. | 05-09-2013 |
20130126890 | INTEGRATING ACTIVE MATRIX INORGANIC LIGHT EMITTING DIODES FOR DISPLAY DEVICES - A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material originally grown thereupon; and bonding the removed layer of inorganic LED material to an active matrix, thin film transistor (TFT) backplane array. | 05-23-2013 |
20130143371 | DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE - Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks. | 06-06-2013 |
20130175596 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer. | 07-11-2013 |
20130178021 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity. | 07-11-2013 |
20130180564 | FIELD-EFFECT PHOTOVOLTAIC ELEMENTS - Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering. | 07-18-2013 |
20130187129 | SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE - A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions. | 07-25-2013 |
20130187171 | METHOD TO FORM SILICIDE CONTACT IN TRENCHES - A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region. | 07-25-2013 |
20130189839 | METHOD TO FORM SILICIDE CONTACT IN TRENCHES - A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region. | 07-25-2013 |
20130193441 | Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer - Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔE | 08-01-2013 |
20130193445 | SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC - Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect. | 08-01-2013 |
20130193482 | Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets - Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔE | 08-01-2013 |
20130193483 | Mosfet Structures Having Compressively Strained Silicon Channel - MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel. | 08-01-2013 |
20130196483 | SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC - Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect. | 08-01-2013 |
20130196486 | Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer - Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔE) between the channel layer and the wide bandgap material is between 0.05 eV and 0.8 eV. The channel layer can be comprised of, for example, In | 08-01-2013 |
20130196488 | Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets - Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔE | 08-01-2013 |
20130240893 | BREAKDOWN VOLTAGE MULTIPLYING INTEGRATION SCHEME - A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both n-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions. | 09-19-2013 |
20130240951 | GALLIUM NITRIDE SUPERJUNCTION DEVICES - Gallium nitride high electron mobility transistor structures enable high breakdown voltages and are usable for high-power, and/or high-frequency switching. Schottky diodes facilitate high voltage applications and offer fast switching. A superjunction formed by p/n junctions in gallium nitride facilitates operation of the high electron mobility transistor structures and Schottky diodes as well as gated diodes formed by drain to gate connections of the transistor structures. Breakdown between the gate and drain of the high electron mobility transistor structures, through the substrate, or both is suppressed. | 09-19-2013 |
20130240993 | FULLY-DEPLETED SON - A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension. | 09-19-2013 |
20130240998 | INTEGRATED CIRCUIT DIODE - A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process. | 09-19-2013 |
20130242627 | MONOLITHIC HIGH VOLTAGE MULTIPLIER - High voltage diode-connected gallium nitride high electron mobility transistor structures or Schottky diodes are employed in a network including high-k dielectric capacitors in a solid state, monolithic voltage multiplier. A superjunction formed by vertical p/n junctions in gallium nitride facilitates operation of the high electron mobility transistor structures and Schottky diodes. A design structure for designing, testing or manufacturing an integrated circuit is tangibly embodied in a machine-readable medium and includes elements of a solid state voltage multiplier. | 09-19-2013 |
20130249004 | Same-Chip Multicharacteristic Semiconductor Structures - In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth. | 09-26-2013 |
20130260505 | SOLAR-POWERED ENERGY-AUTONOMOUS SILICON-ON-INSULATOR DEVICE - A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures. | 10-03-2013 |
20130264612 | DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP - A method for forming a semiconductor device includes forming a gate stack on a monocrystalline substrate. A surface of the substrate adjacent to the gate stack and below a portion of the gate stack is amorphorized. The surface is etched to selectively remove a thickness of amorphorized portions to form undercuts below the gate stack. A layer is epitaxially grown in the thickness and the undercuts to form an extension region for the semiconductor device. Devices are also provided. | 10-10-2013 |
20130264614 | DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP - A method for forming a semiconductor device includes forming a gate stack on a monocrystalline substrate. A surface of the substrate adjacent to the gate stack and below a portion of the gate stack is amorphorized. The surface is etched to selectively remove a thickness of amorphorized portions to form undercuts below the gate stack. A layer is epitaxially grown in the thickness and the undercuts to form an extension region for the semiconductor device. Devices are also provided. | 10-10-2013 |
20130299902 | FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE - A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space. | 11-14-2013 |
20130306971 | SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR - A high resolution active matrix backplane is fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed on a semiconductor-on-insulator substrate. The backplane layer is spalled from the substrate. A frontplane layer including passive devices such as LCDs, OLEDs, photosensitive materials, or piezo-electric materials is formed over the backplane layer to form an active matrix structure. The active matrix structure may be fabricated to allow bottom emission and provide mechanical flexibility. | 11-21-2013 |
20130307078 | SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE - A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions. | 11-21-2013 |
20130309791 | SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR - A high resolution active matrix backplane is fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed on a semiconductor-on-insulator substrate. The backplane layer is spalled from the substrate. A frontplane layer including passive devices such as LCDs, OLEDs, photosensitive materials, or piezo-electric materials is formed over the backplane layer to form an active matrix structure. The active matrix structure may be fabricated to allow bottom emission and provide mechanical flexibility. | 11-21-2013 |
20130313651 | INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES - An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer. | 11-28-2013 |
20130320483 | SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES - Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å. | 12-05-2013 |
20130330887 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 12-12-2013 |
20140048122 | HETEROSTRUCTURE GERMANIUM TANDEM JUNCTION SOLAR CELL - A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer. | 02-20-2014 |
20140048809 | SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR - A high resolution active matrix backplane is fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed on a semiconductor-on-insulator substrate. The backplane layer is spalled from the substrate. A frontplane layer including passive devices such as LCDs, OLEDs, photosensitive materials, or piezo-electric materials is formed over the backplane layer to form an active matrix structure. The active matrix structure may be fabricated to allow bottom emission and provide mechanical flexibility. | 02-20-2014 |
20140060627 | FIELD-EFFECT LOCALIZED EMITTER PHOTOVOLTAIC DEVICE - Photovoltaic structures are provided with field-effect inversion/accumulation layers as emitter layers induced by work-function differences between gate conductor layers and substrates thereof. Localized contact regions are in electrical communication with the gate conductors of such structures for repelling minority carriers. Such localized contact regions may include doped crystalline or polycrystalline silicon regions between the gate conductor and silicon absorption layers. Fabrication of the structures can be conducted without alignment between metal contacts and the localized contact regions or high temperature processing. | 03-06-2014 |
20140070215 | DEFECT FREE STRAINED SILICON ON INSULATOR (SSOI) SUBSTRATES - A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a transfer portion of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer. | 03-13-2014 |
20140073119 | DEFECT FREE STRAINED SILICON ON INSULATOR (SSOI) SUBSTRATES - A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a transfer portion of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer. | 03-13-2014 |
20140091281 | NON-VOLATILE MEMORY DEVICE EMPLOYING SEMICONDUCTOR NANOPARTICLES - Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing. | 04-03-2014 |
20140103422 | STRUCTURE FOR MEMS TRANSISTORS ON FAR BACK END OF LINE - A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level. The MEMS cantilever switch is separated from the gate and the drain by a sacrificial material, which is ultimately removed to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain. | 04-17-2014 |
20140103436 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT - A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates. | 04-17-2014 |
20140103533 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT - A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates. | 04-17-2014 |
20140106494 | DUAL-GATE BIO/CHEM SENSOR - A dual gate extremely thin semiconductor-on-insulator transistor with asymmetric gate dielectrics is provided. This structure can improve the sensor detection limit and also relieve the drift effects. Detection is performed at a constant current mode while the species will be detected at a gate electrode with a thin equivalent oxide thickness (EOT) and the gate bias will be applied to the second gate electrode with thicker EOT to maintain current flow through the transistor. As a result, a small change in the charge on the first electrode with the thin EOT will be translated into a larger voltage on the gate electrode with the thick EOT to sustain the current flow through the transistor. This allows a reduction of the sensor dimension and therefore an increase in the array size. The dual gate structure further includes cavities, i.e., microwell arrays, for chemical sensing. | 04-17-2014 |
20140106552 | Method Of Fabricating MEMS Transistors On Far Back End Of Line - A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level. The MEMS cantilever switch is separated from the gate and the drain by a sacrificial material, which is ultimately removed to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain. | 04-17-2014 |
20140117368 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 05-01-2014 |
20140120666 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 05-01-2014 |
20140131790 | FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES - A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants. | 05-15-2014 |
20140131803 | ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUCTOR DEVICES - An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions | 05-15-2014 |
20140134826 | FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES - A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants. | 05-15-2014 |
20140138773 | DENSE FINFET SRAM - A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features. | 05-22-2014 |
20140138797 | DENSE FINFET SRAM - A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features. | 05-22-2014 |
20140141575 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity. | 05-22-2014 |
20140145254 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - An circuit supporting substrate includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer. | 05-29-2014 |
20140158187 | SELECTIVE EMITTER PHOTOVOLTAIC DEVICE - A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device. | 06-12-2014 |
20140159162 | BULK FINFET WITH SUPER STEEP RETROGRADE WELL - A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor. | 06-12-2014 |
20140159163 | BULK FINFET WITH SUPER STEEP RETROGRADE WELL - A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor. | 06-12-2014 |
20140162396 | SELECTIVE EMITTER PHOTOVOLTAIC DEVICE - A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device. | 06-12-2014 |
20140166079 | MONOLITHIC INTEGRATION OF HETEROJUNCTION SOLAR CELLS - A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure. | 06-19-2014 |
20140166096 | FIELD-EFFECT INTER-DIGITATED BACK CONTACT PHOTOVOLTAIC DEVICE - A method for forming a photovoltaic device includes patterning a dielectric layer on a substrate to form a patterned dielectric having local spacings between shapes and remote spacings between groups of shapes, and depositing a doped epitaxial layer over the patterned dielectric such that selective crystalline growth occurs in portions of the epitaxial layer in contact with the substrate and noncrystalline growth occurs in portions of the epitaxial layer in contact with the patterned dielectric. First metal contacts are formed over the local spacings of the patterned dielectric, and second metal contacts are formed over the remote spacings. Exposed portions of the noncrystalline growth are etched using the first and second metal contacts as an etch mask to form alternating interdigitated emitter and back contact stacks. | 06-19-2014 |
20140170807 | MONOLITHIC INTEGRATION OF HETEROJUNCTION SOLAR CELLS - A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure. | 06-19-2014 |
20140190564 | HETEROJUNCTION III-V SOLAR CELL PERFORMANCE | 07-10-2014 |
20140196773 | MULTI-JUNCTION III-V SOLAR CELL - A multi junction solar cell structure includes a top photovoltaic cell including III-V semiconductor materials and a silicon-based bottom photovoltaic cell. A thin, germanium-rich silicon germanium buffer layer is provided between the top and bottom cells. Fabrication techniques for producing multi junction III-V solar cell structures, lattice-matched or pseudomorphic to germanium, on silicon substrates is further provided wherein silicon serves as the bottom cell. The open circuit voltage of the silicon cell may be enhanced by localized back surface field structures, localized back contacts, or amorphous silicon-based heterojunction back contacts. | 07-17-2014 |
20140196774 | MULTI-JUNCTION III-V SOLAR CELL - A multi junction solar cell structure includes a top photovoltaic cell including III-V semiconductor materials and a silicon-based bottom photovoltaic cell. A thin, germanium-rich silicon germanium buffer layer is provided between the top and bottom cells. Fabrication techniques for producing multi junction III-V solar cell structures, lattice-matched or pseudomorphic to germanium, on silicon substrates is further provided wherein silicon serves as the bottom cell. The open circuit voltage of the silicon cell may be enhanced by localized back surface field structures, localized back contacts, or amorphous silicon-based heterojunction back contacts. | 07-17-2014 |
20140291734 | Thin Channel MOSFET with Silicide Local Interconnect - A semiconductor structure and method of manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate having an isolated area comprising a first region and a second region. A first raised RSD region is formed in the first region and a second RSD region is formed in the second region. The first RSD region and second RSD region is separated laterally by a portion of the isolated area. A continuous silicide interconnect structure is formed overlying the first RSD region, the second RSD region and the portion of the isolated area situated between RSD regions. A contact may be formed on the surface of the silicide interconnect. | 10-02-2014 |
20140353698 | HETEROJUNCTION LIGHT EMITTING DIODE - A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer. | 12-04-2014 |
20140353700 | HETEROJUNCTION LIGHT EMITTING DIODE - A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer. | 12-04-2014 |
20140353726 | LATERAL BIPOLAR TRANSISTORS HAVING PARTIALLY-DEPLETED INTRINSIC BASE - A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode. | 12-04-2014 |
20140357043 | LATERAL BIPOLAR TRANSISTORS HAVING PARTIALLY-DEPLETED INTRINSIC BASE - A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode. | 12-04-2014 |
20140361303 | THIN-FILM HYBRID COMPLEMENTARY CIRCUITS - Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level. | 12-11-2014 |
20140361350 | THIN-FILM HYBRID COMPLEMENTARY CIRCUITS - Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level. | 12-11-2014 |
20140367786 | FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES - Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates. | 12-18-2014 |
20150028289 | ACTIVE MATRIX USING HYBRID INTEGRATED CIRCUIT AND BIPOLAR TRANSISTOR - A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed. | 01-29-2015 |
20150028454 | FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS - Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer. | 01-29-2015 |
20150041824 | TRANSISTOR WITH BONDED GATE DIELECTRIC - A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate. | 02-12-2015 |
20150041826 | TRANSISTOR WITH BONDED GATE DIELECTRIC - A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate. | 02-12-2015 |
20150041936 | PASSIVATION OF BACK-ILLUMINATED IMAGE SENSOR - A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry. | 02-12-2015 |
20150041938 | PASSIVATION OF BACK-ILLUMINATED IMAGE SENSOR - A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry. | 02-12-2015 |
20150050769 | SOLAR-POWERED ENERGY-AUTONOMOUS SILICON-ON-INSULATOR DEVICE - A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures. | 02-19-2015 |
20150059841 | SELECTIVE EMITTER PHOTOVOLTAIC DEVICE - A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device. | 03-05-2015 |
20150069333 | FLEXIBLE ACTIVE MATRIX DISPLAY - High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer. | 03-12-2015 |
Patent application number | Description | Published |
20120112207 | METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE - The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer. | 05-10-2012 |
20120211079 | SILICON PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, and epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 08-23-2012 |
20120255600 | METHOD OF BONDING AND FORMATION OF BACK SURFACE FIELD (BSF) FOR MULTI-JUNCTION III-V SOLAR CELLS - A photovoltaic device including at least one top cell that include at least one semiconductor material; a bottom cell of a germanium containing material having a thickness of 10 microns or less; and a back surface field (BSF) region provided by a eutectic alloy layer of aluminum and germanium on the back surface of the bottom cell of that is opposite the interface between the bottom cell and at least one of the top cells. The eutectic alloy of aluminum and germanium bonds the bottom cell of the germanium-containing material to a supporting substrate. | 10-11-2012 |
20120312362 | SILICON-CONTAINING HETEROJUNCTION PHOTOVOLTAIC ELEMENT AND DEVICE - A photovoltaic device is provided in which the tunneling barrier for hole collection at either the front contact or the back contact of a silicon heterojunction cell is reduced, without compromising the surface passivation either the front contact or at the back contact. This is achieved in the present disclosure by replacing the intrinsic and/or doped hydrogenated amorphous silicon (a-Si:H) layer(s) at the back contact or at the front contact with an intrinsic and/or doped layer(s) of a semiconductor material having a lower valence band-offset than that of a:Si—H with c-Si, and/or a higher activated doping concentration compared to that of doped hydrogenated amorphous Si. The higher level of activated doping is due to the higher doping efficiency of the back contact or front contact semiconductor material compared to that of amorphous Si, and/or modulation doping of the back or front contact semiconducting material. As a result, the tunneling barrier for hole collection is reduced and the cell efficiency is improved accordingly. | 12-13-2012 |
20120329197 | METHOD OF BONDING AND FORMATION OF BACK SURFACE FIELD (BSF) FOR MULTI-JUNCTION III-V SOLAR CELLS - A photovoltaic device including at least one top cell that include at least one III-V semiconductor material; a bottom cell of a germanium containing material having a thickness of | 12-27-2012 |
20120329206 | SILICON-CONTAINING HETEROJUNCTION PHOTOVOLTAIC ELEMENT AND DEVICE - In one embodiment, a method of forming a photovoltaic device is provided which includes providing an absorption layer comprising a silicon-containing semiconductor layer of a first conductivity type and having a top surface and a bottom surface that opposes the top surface. A front contact is formed on the top surface of the absorption layer, and a back contact is formed on the bottom surface of the absorption layer. The forming of the front contact and the back contact can occur in any order. The back contact that is formed comprises at least one back contact semiconductor material layer of the first conductivity type and having a lower band-offset than that of hydrogenated amorphous silicon with crystalline Si and/or a higher activated doping of the first conductivity type than that of the doped hydrogenated amorphous silicon layer. | 12-27-2012 |
20130019944 | METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS - A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material. | 01-24-2013 |
20130019945 | METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS - A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material. | 01-24-2013 |
20130025654 | MULTI-JUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A method of forming a photovoltaic device that includes bonding a substrate to a germanium-containing semiconductor layer with a stressor layer, wherein the stressor layer cleaves the germanium-containing semiconductor layer. At least one semiconductor layer is formed on a cleaved surface of the germanium-containing semiconductor layer that is opposite the conductivity type of the germanium-containing semiconductor layer to provide a first solar cell. The first solar cell absorbs a first range of wavelengths. At least one second solar cell may be formed on the first solar cell, wherein the at least one second solar cell is composed of at least one semiconductor material to absorb a second range of wavelengths that is different than the first range wavelengths absorbed by the first solar cell. | 01-31-2013 |
20130025659 | MULTI-JUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A method of forming a photovoltaic device that includes bonding a substrate to a germanium-containing semiconductor layer with a stressor layer, wherein the stressor layer cleaves the germanium-containing semiconductor layer. At least one semiconductor layer is formed on a cleaved surface of the germanium-containing semiconductor layer that is opposite the conductivity type of the germanium-containing semiconductor layer to provide a first solar cell. The first solar cell absorbs a first range of wavelengths. At least one second solar cell may be formed on the first solar cell, wherein the at least one second solar cell is composed of at least one semiconductor material to absorb a second range of wavelengths that is different than the first range wavelengths absorbed by the first solar cell. | 01-31-2013 |
20130092218 | BACK-SURFACE FIELD STRUCTURES FOR MULTI-JUNCTION III-V PHOTOVOLTAIC DEVICES - A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. | 04-18-2013 |
20130095598 | BACK-SURFACE FIELD STRUCTURES FOR MULTI-JUNCTION III-V PHOTOVOLTAIC DEVICES - A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. | 04-18-2013 |
20130244372 | SILICON PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, and epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 09-19-2013 |
20130307075 | CRYSTALLINE THIN-FILM TRANSISTORS AND METHODS OF FORMING SAME - Thin film transistors containing a gate structure on a crystalline semiconductor material including a crystalline active channel layer are provided. The gate structure of the present disclosure includes an insulator stack of, from bottom to top, a hydrogenated non-crystalline semiconductor material layer portion and a hydrogenated non-crystalline silicon nitride portion. Doped crystalline semiconductor source/drain regions are located on opposing sides of the gate structure and on surface portions of the crystalline semiconductor material. | 11-21-2013 |
20130312819 | REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME - A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell. | 11-28-2013 |
20130313551 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction. | 11-28-2013 |
20130313552 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer. | 11-28-2013 |
20130316488 | REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME - A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell. | 11-28-2013 |
20130316520 | METHODS OF FORMING CONTACT REGIONS USING SACRIFICIAL LAYERS - Methods of patterning semiconductor contact materials on a crystalline semiconductor material which allow high-quality interfaces between the crystalline semiconductor material and the patterned semiconductor contact material are provided. Blanket layers of passivation material and sacrificial material are formed on the crystalline semiconductor material. A first contact opening is formed into the blanker layer of sacrificial material. The first contact opening is extended into blanket layer of passivation material, stopping on a first surface portion of the crystalline semiconductor material, using remaining sacrificial material portions as an etch mask. A semiconductor contact material is formed on the exposed first surface portion of the crystalline semiconductor material. In some embodiments, an electrode material portion can be formed over the first contact opening, and then a second blanket layer of sacrificial material can be formed, followed by forming a next contact opening. | 11-28-2013 |
20130328110 | THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR - Junction field effect transistors are provided which include a gate junction located on a surface of a crystalline semiconductor material of a first conductivity type. The gate junction can be selected from one of a doped hydrogenated crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, a doped hydrogenated non-crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, and a Schottky contact. | 12-12-2013 |
20130341623 | PHOTORECEPTOR WITH IMPROVED BLOCKING LAYER - A photoreceptor includes a multilayer blocking structure to reduce dark discharge of the surface voltage of the photoreceptor resulting from electron injection from an electrically conductive substrate. The multilayer blocking structure includes wide band gap semiconductor layers in alternating sequence with one or more narrow band gap blocking layers. A fabrication method of the photoreceptor includes transfer-doping of the narrow band gap blocking layers, which are deposited in alternating sequence with wide band gap semiconductor layers to form a blocking structure. Suppression of hole or electron injection can be obtained using the method. | 12-26-2013 |
20130341770 | RADIATION HARDENED SOI STRUCTURE AND METHOD OF MAKING SAME - An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact. | 12-26-2013 |
20130344644 | PHOTORECEPTOR WITH IMPROVED BLOCKING LAYER - A photoreceptor includes a multilayer blocking structure to reduce dark discharge of the surface voltage of the photoreceptor resulting from electron injection from an electrically conductive substrate. The multilayer blocking structure includes wide band gap semiconductor layers in alternating sequence with one or more narrow band gap blocking layers. A fabrication method of the photoreceptor includes transfer-doping of the narrow band gap blocking layers, which are deposited in alternating sequence with wide band gap semiconductor layers to form a blocking structure. Suppression of hole or electron injection can be obtained using the method. | 12-26-2013 |
20140000687 | TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD | 01-02-2014 |
20140004654 | TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD | 01-02-2014 |
20140051190 | METHOD OF LARGE-AREA CIRCUIT LAYOUT RECOGNITION - Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce. | 02-20-2014 |
20140077210 | AMORPHOUS SILICON PHOTODETECTOR WITH LOW DARK CURRENT - A p-i-n photodetector includes at least one multilayer contact structure including wide gap and narrow gap layers to reduce dark current. The multilayer contact structure includes one or more wide band gap semiconductor layers in alternating sequence with one or more narrow band gap contact layers. A fabrication method of the photodetector includes transfer-doping of the narrow band gap contact layers, which are deposited in alternating sequence with wide band gap semiconductor layers. | 03-20-2014 |
20140252446 | EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP - A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device. | 09-11-2014 |
20140252448 | EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP - A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device. | 09-11-2014 |
20140367745 | T-SHAPED COMPOUND SEMICONDUCTOR LATERAL BIPOLAR TRANSISTOR ON SEMICONDUCTOR-ON-INSULATOR - A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region. | 12-18-2014 |
20140370683 | T-SHAPED COMPOUND SEMICONDUCTOR LATERAL BIPOLAR TRANSISTOR ON SEMICONDUCTOR-ON-INSULATOR - A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region. | 12-18-2014 |