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| 20090241006 | Bitwise Operations and Apparatus in a Multi-Level System - A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power. | 09-24-2009 |
| 20120079353 | Memory Quality Monitor Based Compensation Method and Apparatus - In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected. | 03-29-2012 |
| 20120272107 | METHOD AND APPARATUS FOR PROVIDING PRELOADED NON-VOLATILE MEMORY CONTENT - An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer. | 10-25-2012 |
| 20130290811 | MEMORY QUALITY MONITOR BASED COMPENSATION METHOD AND APPARATUS - In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected. | 10-31-2013 |
| 20140093076 | BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM - A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power. | 04-03-2014 |
| 20140380123 | MEMORY QUALITY MONITOR BASED COMPENSATION METHOD AND APPARATUS - In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected. | 12-25-2014 |
| 20150194983 | READ THRESHOLD CALIBRATION FOR LDPC - Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified. | 07-09-2015 |
| 20150294737 | METHOD AND APPARATUS FOR PROVIDING PRELOADED NON-VOLATILE MEMORY CONTENT - An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer. | 10-15-2015 |
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| 20110194898 | Slipform Paving Machine With Adjustable Length Tractor Frame - A paving machine that moves in a travel direction and spreads, levels and finishes concrete into a form having a generally upwardly exposed, finished concrete surface that terminates in lateral sides. The paving machine has a main frame with first and second bolsters arranged at opposite ends of the main frame. Each set of bolsters has two hydraulic jacking columns used to raise and lower the machine frame. Crawlers attached to the bottom of the jacking columns engage the ground and move the paving machine in the travel direction. A pair of support beams is attached to the inner surface of each bolster and supported in passageways of a center module of the tractor frame. To extend the maximum width of the paving machine without having to extensively disassemble it, the free ends of the support beams extend beyond outer sides of the bolsters when the distance between the inner sides of the bolsters is at its minimum. This paving machine width adjustment can be performed in the field by moving the bolsters and the support beams attached to them inwardly or outwardly with the crawlers of the paving machine. Also provided is a laterally extendable/retractable cross beam for movably supporting a dowel bar inserter kit on the paving machine. | 08-11-2011 |
| 20110236129 | Adjustable Bolster Swing Legs for Mounting and Aligning and Reorienting Crawlers for Slipform Paving Machines - A paving machine which is configured to move in a paving direction for spreading, leveling and finishing concrete into a form having a generally upwardly exposed, finished concrete surface and terminating in lateral concrete sides. The paving machine has a main frame, including a center module, bolsters laterally movably connected to respective lateral sides of the center module for changing a spacing between the bolsters, and a crawler track associated with respective aft and forward ends of the bolsters. A bolster swing leg for each crawler track supports an upright jacking column secured to the swing leg proximate a free end thereof. A worm gear drive between the jacking column and the crawler track permits rotational movements of the crawler track and the jacking column about an upright axis. A hinge bracket is interposed between each swing leg and an associated surface of the bolsters and includes a fixed, upright pivot shaft that pivotally engages the swing leg to enable pivotal movements of the swing leg about an upright axis in a substantially horizontal plane. The hinge bracket further includes a pivot pin that is laterally spaced from and fixed in relation to the pivot shaft. A length-adjustable holder capable of being held at a fixed length has a first end pivotally engaging the pivot pin on the hinge bracket and a second end that pivotally engages the swing leg. The holder permits pivotal motions of the swing leg about the hinge pin when it is in its length-adjustable configuration and prevents substantially any motion of the swing leg when the holder is in its fixed-length configuration. A feedback loop cooperates with angular position transducers and automatically keeps the crawler tracks oriented in the paving direction of the machine when the swing legs move in a horizontal plane relative to a remainder of the paving machine. The paving machine can be reconfigured between its paving orientation and a road transport orientation by activating the crawlers to move the swing legs and the crawlers into a narrowed transport configuration. | 09-29-2011 |
| 20140161528 | ADJUSTABLE BOLSTER SWING LEGS FOR MOUNTING AND ALIGNING AND REORIENTING CRAWLERS FOR SLIPFORM PAVING MACHINES - A paving machine for spreading, leveling and finishing concrete having a main frame, center module, bolsters laterally movably, and a crawler track associated with respective aft and forward ends of the bolsters. A bolster swing leg for each crawler track supports an upright jacking column. A worm gear drive permits rotational movements of the crawler track and the jacking column. A hinge bracket is interposed between each swing leg and a surface of the bolsters to enable pivotal movements of the swing leg. A length-adjustable holder engages the pivot pin on the hinge bracket and pivotally engages the swing leg. The holder permits pivotal motions of the swing leg in its length-adjustable configuration and prevents substantially any motion of the swing leg in its fixed-length configuration. A feedback loop cooperates with transducers keeping the crawler tracks position. The paving machine can be reconfigured into a narrowed transport configuration. | 06-12-2014 |
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| 20090028574 | SELF-TESTING OPTICAL TRANSCEIVER - Systems and methods for an optical transceiver module to perform one or more diagnostic self-tests without the assistance of a host computing system. The optical transceiver module includes at least one processor, a persistent memory and a system memory. The persistent memory, which is coupled to the at least one processor, contains microcode. The microcode is loaded from the persistent memory to the system memory and executed by the at least one processor. The executed microcode causes the optical transceiver module to perform one or more diagnostic self-tests. The diagnostic result data of the one or more diagnostic self-tests is then stored in the persistent memory and is formatted for analysis. The formatted data may then be analyzed to ascertain the response of the optical transceiver to changes in its test environment. | 01-29-2009 |
| 20090067848 | LIMITED LIFE TRANSCEIVER - Systems and methods for an optical transceiver module to limit the amount of time the optical transceiver module is allowed to operate. The optical transceiver module includes at least one processor, a persistent memory and a system memory. The persistent memory, which is coupled to the at least one processor, contains microcode. The microcode is loaded from the persistent memory to the system memory and executed by the at least one processor. The executed microcode causes the optical transceiver module to detect the amount of time that the optical transceiver has been operating. The optical transceiver module then determines if the detected amount of operating time is in excess of a predetermined amount of operating time. If the detected operating time is in excess of the predetermined amount of operating time, the optical transceiver module causes itself to become non-operational. The optical transceiver module may then report its operational status. | 03-12-2009 |
| 20090138709 | OPTICAL TRANSCEIVER WITH VENDOR AUTHENTICATION - An optical receiver comprising at least one processor and a memory including at least one of an encryption key or a decryption key and at least one of encryption microcode or decryption microcode that includes processor-executable instructions that, when executed by the at least one processor, cause the optical transceiver to perform the following: an act of performing an encryption or decryption operation on data received from a host computing system to thereby authenticate the optical transceiver. | 05-28-2009 |
| 20100254710 | EARLY SELF-VALIDATION OF PERSISTENT MEMORY DURING BOOT IN AN OPTICAL TRANSCEIVER - An operational optical transceiver configured to self-validate a boot image loaded from the persistent memory early in the boot process. The optical transceiver includes a persistent memory, a controller, and a system memory. The controller initializes the boot process and begins to load information from the persistent memory to the system memory. Next, the controller detects early in the boot process boot image verification data in the information being sent to the system memory. The controller then determines if the boot image verification data has an expected value. If the verification data includes the expected value, the controller continues the boot process. If the verification data does not include the expected value, the controller will retry the boot process a predetermined number of times and will enter a default operational state if the expected value is not detected while retrying the boot process the predetermined number of times. | 10-07-2010 |
| 20110010576 | MICROCODE CONFIGURABLE FREQUENCY CLOCK - A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured to receive an input clock signal and to produce an output clock signal by frequency dividing the input signal based on the microcode generated data. The output clock is used to control the speed of comparison in the optical transceiver. | 01-13-2011 |
| 20110020007 | INTER-TRANSCEIVER MODULE COMMUNICATION FOR OPTIMIZATION OF LINK BETWEEN TRANSCEIVERS - Two or more optical transceivers coupled to each other by an optical link to optimize communication over the optical link. A first transceiver generates electrical data that represents an operational parameter for optimization. The transceiver then converts the electrical data into an optical signal and transmits the optical signal over the optical link to a second transceiver. The second transceiver recovers the electrical data from the optical signal and uses the recovered electrical data to change characteristics of the optical signal transmitted by the second transceiver. | 01-27-2011 |
| 20120134680 | INTER-TRANSCEIVER MODULE COMMUNICATION FOR FIRMWARE UPGRADE - An operational optical transceiver configured to update operational firmware using an optical link of the transceiver. The optical transceiver includes at least one processor and a system memory capable of receiving firmware. The optical transceiver receives an optical signal over the optical link containing the update firmware. The optical transceiver then recovers the firmware from the optical signal. Finally, the optical transceiver provides to the system memory the recovered firmware, which when executed by the at least one processor alters the operation of the transceiver. | 05-31-2012 |
| 20130148978 | CHIP IDENTIFICATION PADS FOR IDENTIFICATION OF INTEGRATED CIRCUITS IN AN ASSEMBLY - Chip identification pads for identification of integrated circuits in an assembly. In one example embodiment, an integrated circuit (IC) assembly includes a controller, a plurality of ICs, a shared communication bus connecting the controller to the plurality of ICs and configured to enable communication between the controller and each of the plurality of ICs, and a set of one or more chip identification pads formed on each IC. Each set of chip identification pads has an electrical connection pattern. The electrical connection pattern of each set is distinct from the electrical connection pattern on every other set. Each distinct electrical connection pattern represents a unique identifier of the corresponding IC thereby enabling the controller to distinguish between the ICs. | 06-13-2013 |
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| 20090174434 | DESIGN METHOD AND ARCHITECTURE FOR POWER GATE SWITCH PLACEMENT - A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells. | 07-09-2009 |
| 20090300569 | DESIGN METHOD AND ARCHITECTURE FOR POWER GATE SWITCH PLACEMENT - A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells. | 12-03-2009 |
| 20100063761 | Clock Jitter Analysis - A tool and a method analyze variations in signal timing, especially timing in a clock signal, commonly known as “clock Jitter.” The tool and method provide advantages over conventional analysis approaches, such as comprehensive coverage of all clocks in a design, taking into account all signal coupling effects, ease of use, ability to automatically identify individual jitter sources, and efficient use of computing resources. | 03-11-2010 |
| 20140107999 | MULTI-LEVEL ABSTRACT POWER MODELING METHOD - Methods, apparatuses, and computer readable media for utilizing a single model of event-based energies at multiple hierarchical levels of a design. The event-based energy model contains multiple interfaces that access or reference lower level power data, such as pin-based power data. The power of a transaction level definition of a design is estimated using the event-based energy model. The transaction-level definition of the design uses indirect references to access the event-based energy model. Other abstraction levels of the design may have their power estimated using the same low-level event-based energy model. Overall, a consistent power estimation of a design is performed using the same event-based energy model at different levels of abstraction of the design flow. | 04-17-2014 |
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| 20120184834 | Sensor Catheter Having Reduced Cross-Talk Wiring Arrangements - Improved wiring arrangements for sensor catheters are provided to reduce wire-to-wire cross-talk wherein wires connecting the sensor of the sensor catheter to a processing unit are divided into a plurality of wire bundles contained within respective sheaths, with the wires in wire bundle twisted together reduce electromagnetic signal interference among the individual wires, or between wire bundles. | 07-19-2012 |
| 20140152467 | Medical Communication Hub and Associated Methods - A patient communication system having a medical sensing device operable to collect medical data, a network communication module operable to transmit the medical data onto a data network, a controller operable route the first medical sensing data to the network communication module, and a power source operable to provide power to the first medical sensing device, the controller, and the network communication module. | 06-05-2014 |
| 20140218210 | Medical Communication Hub and Associated Methods - A medical sensing system including a data acquisition module operable to receive patient data from a medical sensing device, the data acquisition module being operable to packetize the patient data, a processing module operable to process the packetized first patient data, a user interface module operable to present the processed packetized patient data within a graphical user interface, and a message queue module in communication with the data acquisition module, processing module, and user interface module, the message queue module being operable to receive the packetized patient data from the modules, temporarily store the packetized patient data, and make the packetized patient data available for retrieval by the modules. | 08-07-2014 |
| 20150025416 | SENSOR CATHETER HAVING REDUCED CROSS-TALK WIRING ARRANGEMENTS - Improved wiring arrangements for sensor catheters are provided to reduce wire-to-wire cross-talk wherein wires connecting the sensor of the sensor catheter to a processing unit are divided into a plurality of wire bundles contained within respective sheaths, with the wires in wire bundle twisted together reduce electromagnetic signal interference among the individual wires, or between wire bundles. | 01-22-2015 |
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| 20080295330 | Method and process for manufacturing a terminal block - A method of manufacturing a terminal block for a telecommunication cable comprising the steps of providing a preformed substrate member comprising a podium member, at least one electrical connector and at least one insulated electrical wire attached to an electrical contact positioned within the at least one electrical connector; placing the preformed substrate member in a mold; and injecting a dielectric material into the mold containing the podium member to form an overmolded terminal block, wherein the dielectric material covers the at least one insulated electrical wire and a portion of the electrical contact positioned within the at least one electrical connector. | 12-04-2008 |
| 20090304341 | SEALING GLAND SYSTEM - A sealing gland system having an upper half, a lower half, and a sealing material positioned between the upper and lower halves. Each of the upper and lower halves and the sealing material has at least one opening extending therethrough, and wherein the sealing material forms a seal around at least one cable extending through the sealing material upon compression thereof. | 12-10-2009 |
| 20100269340 | METHOD AND PROCESS FOR MANUFACTURING A TERMINAL BLOCK - A method of manufacturing a terminal block for a telecommunication cable comprising the steps of providing a preformed substrate member comprising a podium member, at least one electrical connector and at least one insulated electrical wire attached to an electrical contact positioned within the at least one electrical connector; placing the preformed substrate member in a mold; and injecting a dielectric material into the mold containing the podium member to form an overmolded terminal block, wherein the dielectric material covers the at least one insulated electrical wire and a portion of the electrical contact positioned within the at least one electrical connector. | 10-28-2010 |
| 20110268416 | SEALING GLAND SYSTEM - A sealing gland system having an upper half, a lower half, and a sealing material positioned between the upper and lower halves. Each of the upper and lower halves and the sealing material has at least one opening extending therethrough, and wherein the sealing material forms a seal around at least one cable extending through the sealing material upon compression thereof. | 11-03-2011 |
| 20110272894 | SEALING GLAND SYSTEM - A sealing gland system having an upper half, a lower half, and a sealing material positioned between the upper and lower halves. Each of the upper and lower halves and the sealing material has at least one opening extending therethrough, and wherein the sealing material forms a seal around at least one cable extending through the sealing material upon compression thereof. | 11-10-2011 |
| 20140101936 | METHOD AND PROCESS FOR MANUFACTURING A TERMINAL BLOCK - A method of manufacturing a terminal block for a telecommunication cable is disclosed, which includes providing a preformed substrate member comprising an elongated podium member having a plurality of wire receiving slots on an outer edge of the podium member and a plurality of electrical connector slots positioned within the podium member, wherein the plurality of wire receiving slots are arranged in pairs having a first and a second wire receiving slot, which are configured to receive one wire each of a pair of insulated electrical wires, an electrical connector in each of the plurality of electrical connector slots, each electrical connector having a pair of electrical contacts extending therefrom, and at least one insulated electrical wire attached to a first end of each of the electrical contacts; placing the substrate member in a mold; and injecting a dielectric material by a force of greater than | 04-17-2014 |
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| 20090243284 | Fluid Transfer Assemblies and Related Methods - An assembly includes a first polymeric connector having a first passageway and a second passageway fixed relative to the first passageway; a first polymeric conduit having a third passageway in fluid communication with the first passageway; and a polymeric member extending over a gap between the first connector and the first conduit and at least portions of outer surfaces of the first connector and the first conduit. A method of attaching a first polymeric connector having a first passageway and a second passageway fixed relative to the first passageway, and a first polymeric conduit having a third passageway, the method includes attaching the first polymeric connector to the first polymeric conduit with a polymeric member extending over at least portions of outer surfaces of the first connector and the first conduit. The first passageway is in fluid communication with the third passageway. | 10-01-2009 |
| 20110241262 | FLEXIBLE TUBING MATERIAL AND METHOD OF FORMING THE MATERIAL - A flexible tubing material includes a radiation crosslinked blend of a first elastomeric polymer including a styrenic thermoplastic elastomer, an ethylene vinyl acetate elastomer, a polyolefin elastomer with a second elastomeric polymer including a polyolefin elastomer, a diene elastomer, or combination thereof, with the proviso that the first elastomeric polymer and the second elastomeric polymer are different. In an embodiment, a method of making a material includes providing the first elastomeric polymer, providing the second elastomeric polymer, blending the first elastomeric polymer and the second elastomeric polymer, extruding or injection molding the blend, and crosslinking the blend with radiation. | 10-06-2011 |
| 20150337126 | FLEXIBLE TUBING MATERIAL AND METHOD OF FORMING THE MATERIAL - A flexible tubing material includes a radiation crosslinked blend of a first elastomeric polymer including a styrenic thermoplastic elastomer, an ethylene vinyl acetate elastomer, a polylefin elastomer with a second elastomeric polymer including a polyolefin elastomer, a diene elastomer, or combination thereof, with the proviso that the first elastomeric polymer and the second elastomeric polymer are different. In an embodiment, a method of making a material includes providing the first elastomeric polymer, providing the second elastomeric polymer, blending the first elastomeric polymer and the second elastomeric polymer, extruding or injection molding the blend, and crosslinking the blend with radiation. | 11-26-2015 |
