| Patent application number | Description | Published |
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| 20100074028 | Memory Architecture Having Two Independently Controlled Voltage Pumps - In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell. | 03-25-2010 |
| 20120188826 | MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS - In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell. | 07-26-2012 |
| 20130141978 | FLASH MEMORY DEVICES AND SYSTEMS - Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations. | 06-06-2013 |
| 20130170292 | HIGH VOLTAGE TOLERANT ROW DRIVER - A circuit is configured to supply a first gate voltage (PG | 07-04-2013 |
| 20140301139 | Method to Reduce Program Disturbs in Non-Volatile Memory Cells - A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V | 10-09-2014 |
| 20140369136 | SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES - Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device. | 12-18-2014 |
| Patent application number | Description | Published |
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| 20080238513 | Hysteresis Circuit Without Static Quiescent Current - A hysteresis circuit including a comparator and capacitive voltage divider circuit. The capacitive voltage divider circuit includes a first capacitor coupled between an input terminal and a positive comparator input, a second capacitor coupled between ground and the positive comparator input, and a third capacitor coupled between the comparator output and positive comparator input. A reference voltage is applied to the negative comparator input. The comparator is powered by the input signal provided on the input terminal. When the voltage on the positive comparator input is less than the reference voltage, the third capacitor is effectively coupled in parallel with the first capacitor. When the voltage on the positive comparator input is greater than the reference voltage, the third capacitor is effectively coupled in parallel with the second capacitor. | 10-02-2008 |
| 20080242027 | Non-Volatile Memory Integrated Circuit - A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell. | 10-02-2008 |
| 20080278346 | Single-Pin Multi-Bit Digital Circuit Configuration - According to some embodiments, a single-pin method of configuring a multi-bit state of a state machine of a circuit comprises: connecting a configuration resistor load having a configuration resistance to a single input pin of the integrated circuit; injecting a configuration current through the input pin and configuration resistor load; in response to injecting the current, generating a sequence of configuration signals indicative of a plurality of results of a plurality of comparisons of the configuration resistance to a plurality of predetermined thresholds, each result corresponding to a threshold; and configuring the multi-bit state of the state machine according to the sequence of configuration signals. | 11-13-2008 |
| 20080291729 | Non-Volatile Memory With High Reliability - A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced. | 11-27-2008 |
| 20090003074 | Scalable Electrically Eraseable And Programmable Memory (EEPROM) Cell Array - A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V | 01-01-2009 |
| 20090135649 | Scalable Electrically Eraseable And Programmable Memory (EEPROM) Cell Array - A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V | 05-28-2009 |
| 20090196105 | Scalable Electrically Eraseable And Programmable Memory (EEPROM) Cell Array - A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V | 08-06-2009 |
| 20120140565 | Scalable Electrically Eraseable And Programmable Memory - A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor. | 06-07-2012 |
