Patent application number | Description | Published |
20090006379 | FILTERING METHOD AND SYSTEM FOR THE CORRELATION BETWEEN TESTING OBJECTS AND PATENTS - In a filtering system for a correlation related to a composing element portfolio of a patent, a plurality of elements are defined by standard element codes and stored. Then composing elements of the patent are defined by the corresponding standard element codes in a standard element depository so as to form the composing element portfolio of the patent to be stored. Then an input module defines a composing element portfolio of the testing object according to the standard element codes. After that, the composing element portfolio input by the input module is matched with the composing element portfolio of each said patent. Afterward, matching result are sorted according to correlation and a sorted result based on the correlation is displayed. | 01-01-2009 |
20090072361 | Multi-Chip Stacked Package Structure - A multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel; a first chip fixedly connected to the back surface of the lead-frame, and the first chip having an active surface and a plurality of first pads adjacent to the central area of the active surface; a plurality of first metal wires electrically connected the first inner leads and the second inner leads and the first pads on the active surface of the first chip; a second chip fixedly connected to the top surface of the lead-frame, and the second chip having an active surface and a plurality of second pads adjacent to the central area of the active surface; a pair of the spacers provided on the thermal fin of the lead-frame; a plurality of second metal wires electrically connected to the top surface of first inner leads and the second inner leads and the second pads on the active surface of the second chip; and a package body encapsulated the first chip, the plurality of metal wires the second chip, the plurality of pads, the first inner leads and the second inner leads and to expose the outer leads. | 03-19-2009 |
20090075426 | Method for Fabricating Multi-Chip Stacked Package - A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing a first chip on the reverse surface of the lead frame and the active surface of the first chip includes a plurality of first pads closed to the central region; forming a plurality of first metal wires, and the first pads are electrically connected to the first inner leads and the second inner leads by the first metal wires; forming a plurality of metal spacers on the thermal fin of the lead frame; fixing a second chip to electrically connect to the top surface of the first inner leads and the second inner leads; forming a plurality of second metal wires, and the second pads are electrically connected to the top surface of the first inner leads and the second inner leads; and flowing a molding to form an encapsulated material to cover the first chip, the first metal wires, the second chip, the second metal wires, the first inner leads and the second inner leads and the outer leads being exposed. | 03-19-2009 |
20090158254 | AUTOMATIC CREATIVE PROPOSAL GENERATING AND FILTERING SYSTEM AND MANUFACTURING METHOD THEREOF AND MULTIPLE COMPONENTS COMBINING METHOD - The present invention discloses an automatic method and system for generating and filtering out the innovation proposals. Particularly, it is about a system, which generates all the possible element code sets, compares them to the code sets of existing objects or documents, and then filters out the novel element code sets. The system comprises a standard element depository, a permutation and combination module, a testing object processing module, a matching module, a sifting module, and an output module. | 06-18-2009 |
20090160043 | Dice Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration - A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material. | 06-25-2009 |
20090160071 | Die rearrangement package structure using layout process to form a compliant configuration - A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material. | 06-25-2009 |
20090230527 | Multi-chips package structure and the method thereof - A multi-chips package structure is provided, which includes a chip-placed frame having a plurality of chip-placed areas thereon, and two adjacent chip-placed areas is connected by a plurality of leads; a plurality of chips, each chip has a plurality of pads on an active surface thereon, and is provided on the chip-placed area; a package body is covered around the four sides of the chip-placed frame, and the pads of the chip is to be exposed; one end of a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended to cover the surface of the patterned first protection layer; a patterned second protective layer is covered on the patterned metal traces and another end of the patterned metal traces is to be exposed; a plurality of patterned UMB layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UMB layer and is electrically connected to one end of the exposed portion of the patterned metal traces. | 09-17-2009 |
20090236703 | Chip package structure and the method thereof - A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces. | 09-24-2009 |
20100006997 | Chip-Stacked Package Structure with Leadframe Having Multi-Piece Bus Bar - The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces. | 01-14-2010 |
20100084759 | Die Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration - A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material. | 04-08-2010 |
20100155916 | CHIP PACKAGE STRUCTURE AND THE METHOD THEREOF WITH ADHERING THE CHIPS TO A FRAME AND FORMING UBM LAYERS - A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces. | 06-24-2010 |
20100264527 | Stacked Chip Package Structure with Leadframe Having Bus Bar - The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad. | 10-21-2010 |
20100264530 | Stacked Chip Package Structure with Leadframe Having Bus Bar - The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad. | 10-21-2010 |
20100314729 | Stacked Chip Package Structure with Leadframe Having Inner Leads with Transfer Pad - The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offest chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer. | 12-16-2010 |
20110163426 | Dice Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration - A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material. | 07-07-2011 |
20110183466 | PACKAGING METHOD INVOLVING REARRANGEMENT OF DICE - A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice. | 07-28-2011 |