Patent application number | Description | Published |
20130166939 | APPARATUS, SYSTEM, AND METHOD FOR PROVIDING CLOCK SIGNAL ON DEMAND - Described herein are apparatus, system, and method for providing clock signal on demand. The method comprises determining an indication of clock signal usage in multiple hardware logic units; generating an enable signal according to the indication; and gating or un-gating the clock signal for clock islands of at least a hardware logic unit, of the multiple hardware logic units, in response to a logic level of the enable signal, wherein the clock islands are part of a global clock distribution network and are operable to be enabled or disabled independently. | 06-27-2013 |
20130262826 | APPARATUS AND METHOD FOR DYNAMICALLY MANAGING MEMORY ACCESS BANDWIDTH IN MULTI-CORE PROCESSOR - An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature. | 10-03-2013 |
20140006904 | ENCODING INFORMATION IN ERROR CORRECTING CODES | 01-02-2014 |
20140189472 | EFFICIENT CACHE SEARCH AND ERROR DETECTION - A first codeword may be constructed from a cache tag in a cache and an error correction code corresponding to the cache tag. A second codeword may be constructed from a search tag and an error correction code corresponding to the search tag. A hamming distance may be calculated between the first codeword and the second codeword. If the hamming distance is less than or equal to a threshold, a cache hit may be signaled. If the hamming distance is above the threshold, a cache miss may be signaled. | 07-03-2014 |
20140189473 | Apparatus and Method For Fast Tag Hit With Double Error Correction and Triple Error Detection - A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by determining if said hamming distance is two or less. | 07-03-2014 |
20140258618 | MULTI LATENCY CONFIGURABLE CACHE - Described herein are technologies for optimizing different cache configurations of a size-configurable cache. One configuration includes a base cache portion and a removable cache portion, each with different latencies. The latency of the base cache portion is modified to correspond to the latency of the removable portion. | 09-11-2014 |
20140281239 | ADAPTIVE HIERARCHICAL CACHE POLICY IN A MICROPROCESSOR - A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy. | 09-18-2014 |
20140359330 | REDUCED POWER MODE OF A CACHE UNIT - In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed. | 12-04-2014 |
20140380081 | Restricting Clock Signal Delivery In A Processor - In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed. | 12-25-2014 |
20150033051 | Restricting Clock Signal Delivery Based On Activity In A Processor - In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed. | 01-29-2015 |
20150095674 | Utilization of Processor Capacity at Low Operating Frequencies - In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed. | 04-02-2015 |
20150149800 | PERFORMING AN OPERATING FREQUENCY CHANGE USING A DYNAMIC CLOCK CONTROL TECHNIQUE - In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation circuit to receive and distribute a first clock signal at a first operating frequency provided from a phase lock loop of the processor to a plurality of units of the core. The clock generation circuit may include a dynamic clock logic to receive a dynamic clock frequency command and to cause the clock generation circuit to distribute the first clock signal to at least one of the units at a second operating frequency. Other embodiments are described and claimed. | 05-28-2015 |
20150177799 | METHOD AND APPARATUS TO CONTROL CURRENT TRANSIENTS IN A PROCESSOR - In an embodiment, a processor includes a first core that includes an execution unit, counter logic, and control logic. The counter logic is to determine a first sum of power weights of a first plurality of instructions to be executed by the execution unit in a first time period, where each power weight is assigned to a corresponding instruction and each power weight is determined independent of an instruction width of the corresponding instruction. The control logic is to request a first current protection license based on the first sum of power weights. Other embodiments are described and claimed. | 06-25-2015 |
20150280748 | DOUBLE CONSECUTIVE ERROR CORRECTION - Double consecutive error correction is described. An integrated circuit with double consecutive error correction logic includes a data storage structure operative to store a set of data and a first error correction code that corresponds to the set of data. The set of data includes multiple data bits. The first error correction code was generated using a generator matrix having multiple bit groups, each bit group including a unique set of bit positions. The integrated circuit also includes an error correction code generator operative to generate, using the generator matrix, a second error correction code that corresponds to the set of data. The integrated circuit further includes a comparator operative to generate a comparison result of the first error correction code and the second error correction code. The integrated circuit includes a data corrector operative to correct two consecutive data bits of the set of data. | 10-01-2015 |
20150355705 | Forcing A Processor Into A Low Power State - In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed. | 12-10-2015 |
20160085675 | Utilization of Processor Capacity at Low Operating Frequencies - In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed. | 03-24-2016 |
20160092357 | Apparatus and Method to Transfer Data Packets between Domains of a Processor - In an embodiment, a processor includes a first domain to operate according to a first clock. The first domain includes a write source, a payload bubble generator first in first out buffer (payload BGF) to store data packets, and write credit logic to maintain a count of write credits. The processor also includes a second domain to operate according to a second clock. When the write source has a data packet to be stored while the second clock is shut down, the write source is to write the data packet to the payload BGF responsive to the count of write credits being at least one, and after the second clock is restarted the second domain is to read the data packet from the payload BGF. Other embodiments are described and claimed. | 03-31-2016 |
Patent application number | Description | Published |
20140027344 | METHODS AND SYSTEMS FOR UPGRADING HEAVY OIL USING CATALYTIC HYDROCRACKING AND THERMAL COKING - Methods and systems for hydroprocessing heavy oil feedstocks to form upgraded material use a colloidal or molecular catalyst dispersed within heavy oil feedstock, pre-coking hydrocracking reactor, separator, and coking reactor. The colloidal or molecular catalyst promotes upgrading reactions that reduce the quantity of asphaltenes or other coke forming precursors in the feedstock, increase hydrogen to carbon ratio in the upgraded material, and decrease boiling points of hydrocarbons in the upgraded material. The methods and systems can be used to upgrade vacuum tower bottoms and other low grade heavy oil feedstocks. The result is one or more of increased conversion level and yield, improved quality of upgraded hydrocarbons, reduced coke formation, reduced equipment fouling, processing of a wider range of lower quality feedstocks, and more efficient use of supported catalyst if used with the colloidal or molecular catalyst, as compared to a conventional hydrocracking process or a conventional thermal coking process. | 01-30-2014 |
20150361360 | APPARATUS AND SYSTEMS FOR UPGRADING HEAVY OIL USING CATALYTIC HYDROCRACKING AND THERMAL COKING - Methods and systems for hydroprocessing heavy oil feedstocks to form an upgraded material involve the use of a colloidal or molecular catalyst dispersed within a heavy oil feedstock, a pre-coking hydrocracking reactor, a separator, and a coking reactor. The colloidal or molecular catalyst promotes upgrading reactions that reduce the quantity of asphaltenes or other coke forming precursors in the feedstock, increase hydrogen to carbon ratio in the upgraded material, and decrease boiling points of hydrocarbons in the upgraded material. The methods and systems can be used to upgrade vacuum tower bottoms and other low grade heavy oil feedstocks. The result is one or more of increased conversion level and yield, improved quality of upgraded hydrocarbons, reduced coke formation, reduced equipment fouling, processing of a wider range of lower quality feedstocks, and more efficient use of supported catalyst if used in combination with the colloidal or molecular catalyst, as compared to a conventional hydrocracking process or a conventional thermal coking process. | 12-17-2015 |
Patent application number | Description | Published |
20100079850 | MAGNETOPHORETIC AND ELECTROMAGNETOPHORETIC DISPLAYS - The present invention is directed to a display device which comprises two layers of insulating substrate, at least the substrate on the viewing side is transparent, an array of display cells sandwiched between the two layers of substrate, a writing means, and optionally an erasing means to magnetically or electrically erase the image. The display cells are filled with a dispersion of magnetic particles which may be charged or non-charged. The display of the invention eliminates the use of the transparent conductor film, such as ITO, on the viewing side. Therefore, the displays of this invention are more cost effective, more flexible and durable and capable of higher image contrast ratio and higher reflectance in the Dmin area. | 04-01-2010 |
20110292495 | MAGNETOPHORETIC AND ELECTROMAGNETOPHORETIC DISPLAYS - The present invention is directed to a display device which comprises two layers of insulating substrate, at least the substrate on the viewing side is transparent, an array of display cells sandwiched between the two layers of substrate, a writing means, and optionally an erasing means to magnetically or electrically erase the image. The display cells are filled with a dispersion of magnetic particles which may be charged or non-charged. The display of the invention eliminates the use of the transparent conductor film, such as ITO, on the viewing side. Therefore, the displays of this invention are more cost effective, more flexible and durable and capable of higher image contrast ratio and higher reflectance in the Dmin area. | 12-01-2011 |
Patent application number | Description | Published |
20090150518 | Dynamic content assembly on edge-of-network servers in a content delivery network - The present invention enables a content provider to dynamically assemble content at the edge of the Internet, preferably on content delivery network (CDN) edge servers. Preferably, the content provider leverages an “edge side include” (ESI) markup language that is used to define Web page fragments for dynamic assembly at the edge. Dynamic assembly improves site performance by catching the objects that comprise dynamically generated pages at the edge of the Internet, close to the end user. The content provider designs and develops the business logic to form and assemble the pages, for example, by using the ESI language within its development environment. Instead of being assembled by an application/web server in a centralized data center, the application/web server sends a page template and content fragments to a CDN edge server where the page is assembled. Each content fragment can have its own cacheability profile to manage the “freshness” of the content. Once a user requests a page (template), the edge server examines its cache for the included fragments and assembles the page on-the-fly. | 06-11-2009 |
20100274819 | Dynamic content assembly on edge-of-network servers in a content delivery network - The disclosed technique enables a content provider to dynamically assemble content at the edge of the Internet, preferably on content delivery network (CDN) edge servers. Preferably, the content provider leverages an “edge side include” (ESI) markup language that is used to define Web page fragments for dynamic assembly at the edge. Dynamic assembly improves site performance by catching the objects that comprise dynamically generated pages at the edge of the Internet, close to the end user. The content provider designs and develops the business logic to form and assemble the pages, for example, by using the ESI language within its development environment. Instead of being assembled by an application/web server in a centralized data center, the application/web server sends a page template and content fragments to a CDN edge server where the page is assembled. Each content fragment can have its own cacheability profile to manage the “freshness” of the content. Once a user requests a page (template), the edge server examines its cache for the included fragments and assembles the page on-the-fly. | 10-28-2010 |
20120203873 | Dynamic content assembly on edge-of-network servers in a content delivery network - Content is dynamically assembled at the edge of the Internet, preferably on content delivery network (CDN) edge servers. A content provider leverages an “edge side include” (ESI) markup language that is used to define Web page fragments for dynamic assembly at the edge. Dynamic assembly improves site performance by caching objects that comprise dynamically-generated pages at the edge of the Internet, close to the end user. Instead of being assembled by an application/web server in a centralized data center, the application/web server sends a page template and content fragments to a CDN edge server where the page is assembled. Each content fragment can have its own cacheability profile to manage the “freshness” of the content. Once a user requests a page, the edge server examines its cache for the included fragments and assembles the page on-the-fly. | 08-09-2012 |