Patent application number | Description | Published |
20120280326 | Method for Manufacturing a Hybrid MOSFET Device and Hybrid MOSFET Obtainable Thereby - Disclosed are methods for forming hybrid metal-oxide-semiconductor field effect transistors (MOSFETs) and the hybrid MOSFETS thus obtained. In one embodiment, a method is disclosed that includes providing a first substrate comprising a first region and a second region, providing a second substrate comprising a second semiconductor layer and an insulating layer overlaying the second semiconductor layer, and direct substrate bonding the second substrate to the first substrate, thereby contacting the first region and the second region with the insulating layer. The method further includes selectively removing the second semiconductor layer and the insulating layer in the first region, thereby exposing the first semiconductor layer in the first region, forming a first gate stack of a first MOSFET on the exposed first semiconductor layer in the first region, and forming a second gate stack of a second MOSFET on the second semiconductor layer in the second region. | 11-08-2012 |
20130161588 | Implant Free Quantum Well Transistor, Method for Making Such an Implant Free Quantum Well Transistor and Use of Such an Implant Free Quantum Well Transistor - An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region. | 06-27-2013 |
20130181301 | METHOD FOR MANUFACTURING A FIELD-EFFECT SEMICONDUCTOR DEVICE FOLLOWING A REPLACEMENT GATE PROCESS - A method of manufacturing a semiconductor device is disclosed. In one aspect, the method includes: forming a dummy gate over a substrate layer; forming first gate insulating spacers adjacent to sidewalls of the dummy gate and over the substrate layer, the first spacers having two sidewalls and two surface profiles where the sidewalls meet the substrate layer; forming a source and drain region using the surface profiles; forming second gate insulating spacers adjacent to the sidewalls of the first spacers and over the source and drain regions; removing the dummy gate and the first spacers, thereby forming a first recess; depositing a dielectric layer in the first recess along the side walls of the second spacers and over the substrate layer, thereby forming a second recess; and depositing a gate electrode in the second recess. | 07-18-2013 |
20140054547 | DEVICE WITH STRAINED LAYER FOR QUANTUM WELL CONFINEMENT AND METHOD FOR MANUFACTURING THEREOF - The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer. | 02-27-2014 |
20140077332 | Band Engineered Semiconductor Device and Method for Manufacturing Thereof - The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted āVā band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device. | 03-20-2014 |
20140124894 | SEMICONDUCTOR DEVICE COMPRISING A DIODE AND A METHOD FOR PRODUCING SUCH A DEVICE - The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion. In another aspect, a method of fabrication the device does not require a separate ESD implant for lowering the holding voltage and can allow for a reduction in the number of processing steps as well as other devices comprising a diode junction. | 05-08-2014 |
20140138787 | Avalanche Photodetector Element - An avalanche photodetector element is disclosed for converting an optical signal to an electrical signal, comprising an input waveguide and a photodetector region, the photodetector region comprising at least one intrinsic region, at least one p-doped region and at least one n-doped region, the doped regions and the at least one intrinsic region forming at least one PIN-junction avalanche photodiode, the input waveguide and the photodetector region being arranged with respect to each other such that the optical signal conducted by the input waveguide is substantially conducted into the photodetector region to the PIN-junction avalanche photodiode, the PIN-junction avalanche photodiode converting the optical signal to an electrical signal, characterized in that the photodetector region comprises more than one p-doped region and/or n-doped region, whereby these p-doped regions and/or n-doped regions are physically arranged as an array. | 05-22-2014 |
20150126010 | Band Engineered Semiconductor Device and Method for Manufacturing Thereof - The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted āVā band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device. | 05-07-2015 |