Patent application number | Description | Published |
20090258503 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND COMPUTER READABLE MEDIUM FOR STORING PATTERN SIZE SETTING PROGRAM - A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps. | 10-15-2009 |
20100003819 | DESIGN LAYOUT DATA CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A design layout data creating method includes creating design layout data of a semiconductor device such that patterns formed on a wafer when patterns corresponding to the design layout data are formed on the wafer have a pattern coverage ratio within a predetermined range in a wafer surface and total peripheral length of the patterns formed on the wafer when the patterns corresponding to the design layout are formed on the wafer is pattern peripheral length within a predetermined range. | 01-07-2010 |
20100035168 | PATTERN PREDICTING METHOD, RECORDING MEDIA AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A pattern predicting method according to one embodiment includes obtaining shape data of a target pattern from shape data of a second pattern to be formed by transferring a first pattern at predetermined process conditions by using a first neutral network, the target pattern being to be a target of the second pattern when the first pattern is transferred at the predetermined process conditions, so as to keep the transferred patterns within an acceptable range, the transferred patterns being formed by transferring the first pattern at process conditions changed from the predetermined process conditions and obtaining shape data of a new first pattern for forming the target pattern at the predetermined process conditions by using a second neutral network. | 02-11-2010 |
20100241261 | PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT - Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result. | 09-23-2010 |
20110047518 | PATTERN DETERMINING METHOD - According to the embodiments, a first representative point is set on outline pattern data on a pattern formed in a process before a processed pattern. Then, a minimum distance from the first representative point to a peripheral pattern is calculated. Then, area of a region with no pattern, which is sandwiched by the first representative point and the peripheral pattern, in a region within a predetermined range from the first representative point is calculated. Then, it is determined whether the first representative point becomes a processing failure by using the minimum distance and the area. | 02-24-2011 |
20110065030 | MASK PATTERN DETERMINING METHOD, MASK MANUFACTURING METHOD, AND DEVICE MANUFACTURING METHOD - According to one embodiment, a mask pattern determining method includes a mask-pattern dimension variation amount of a first photomask is derived. Moreover, a correspondence relationship between a target dimension value of an on-substrate test pattern formed by using a second photomask and a dimension allowable variation amount of a mask pattern formed on the second photomask is derived. Then, it is determined whether pattern formation is possible with a pattern dimension that needs to be formed when performing the pattern formation on a substrate by using the first photomask based on the mask-pattern dimension variation amount and the correspondence relationship. | 03-17-2011 |
20110307845 | PATTERN DIMENSION CALCULATION METHOD AND COMPUTER PROGRAM PRODUCT - A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position. | 12-15-2011 |
20120183906 | MASK PATTERN GENERATING METHOD, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT - According to a mask pattern generating method of the embodiments, an undesired pattern, which is transferred onto a substrate due to an auxiliary pattern when an on-substrate pattern is formed on the substrate by using a mask pattern in which the auxiliary pattern is placed, is extracted as an undesired transfer pattern. Then, the mask pattern is corrected by changing a size of the auxiliary pattern according to a size and a position of the undesired transfer pattern. | 07-19-2012 |
20120184109 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND COMPUTER READABLE MEDIUM FOR STORING PATTERN SIZE SETTING PROGRAM - A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps. | 07-19-2012 |
20120246601 | PATTERN CORRECTING METHOD, MASK FORMING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area. | 09-27-2012 |
20120311511 | MASK INSPECTION METHOD, MASK PRODUCTION METHOD, SEMICONDUCTOR DEVICE PRODUCTION METHOD, AND MASK INSPECTION DEVICE - A mask inspection method according to the embodiments, original data corresponding to a semiconductor integrated circuit pattern to be formed on a substrate is created. After that, original production simulation which mocks an original production process is performed on the original data to derive information relating to an original pattern shape in the case of forming an original pattern corresponding to the original data on an original. After that, whether or not the information relating to an original pattern shape satisfies a predetermined value decided based on the original production process is determined. | 12-06-2012 |
20140059502 | PATTERN DATA GENERATION METHOD, PATTERN VERIFICATION METHOD, AND OPTICAL IMAGE CALCULATION METHOD - According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected. | 02-27-2014 |
Patent application number | Description | Published |
20090186424 | PATTERN GENERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled. | 07-23-2009 |
20100081265 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns. | 04-01-2010 |
20100168895 | MASK VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER READABLE MEDIUM - A mask verification method includes setting optical parameters, verifying whether a pattern, which is obtained when a mask pattern other than a reference pattern of patterns on a mask is transferred on a substrate with use of the set optical parameters, satisfies dimensional specifications, and varying, when the pattern which is obtained when the mask pattern is transferred on the substrate is determined to fail to satisfy the dimensional specifications, the optical parameters at the time of transfer such that the pattern, which is obtained when the reference pattern is transferred on the substrate, satisfies a target dimensional condition, and verifying whether a pattern, which is obtained when the mask pattern other than the reference pattern of the patterns on the mask is transferred on the substrate with use of the varied optical parameters, satisfies the dimensional specifications. | 07-01-2010 |
20100314771 | SEMICONDUCTOR DEVICE INCLUDING AN IMPROVED LITHOGRAPHIC MARGIN - A semiconductor device includes first to third lines. The second line has a width equal to the first line. The second line is arranged with a space equal to the width from the first line, and partially has a gap. The third line is connected to one end of the first line and to a side of one end of the second line. | 12-16-2010 |
20120106282 | PATTERN LAYOUT IN SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch. An interval between the line in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below. | 05-03-2012 |
20120241834 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1) | 09-27-2012 |
20130111416 | DESIGN DATA OPTIMIZATION METHOD, STORAGE MEDIUM INCLUDING PROGRAM FOR DESIGN DATA OPTIMIZATION METHOD AND PHOTOMASK MANUFACTURING METHOD | 05-02-2013 |
20140017887 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1) | 01-16-2014 |