Patent application number | Description | Published |
20080223748 | Rotating Egg Container - A rotating egg container is disclosed having a body and an internal rotating unit for storing a plurality of eggs. The internal rotating unit has a plurality of egg holding sections joined to two opposing tracks defining a pathway through which the egg holding sections can be moved. | 09-18-2008 |
20080237229 | Telescoping Egg Container - A telescoping egg container is disclosed comprising a plurality of slidable egg holder units that can nest one within another, such that the telescoping egg container can be extended or collapsed to accommodate various numbers of eggs to be stored. | 10-02-2008 |
20100050394 | Releasable Pull Tie - A pull tie is described comprising an elastomeric cord and a slidable stop. The pull tie can be suitable for releasable, multi-use closures for flexible bags and containers. | 03-04-2010 |
20120198971 | Knot Loosening Device - A knot loosening device and method of use. A pointed member is disposed, for inserting into the knot, followed by a midsection with a pry arm. Once the midsection is engaged, the pry arm is actuated by means of a lever arm which can be viewed as outwardly expanding jaws or jaw surfaces which have the effect of spreading or loosening the knot. | 08-09-2012 |
20130167329 | Releasable Pull Tie - A pull tie is described having an elastomeric cord and a slidable stop. The pull tie can be suitable for releasable, multi-use closures for flexible bags and containers. The pull tie can be opened and closed with one hand. | 07-04-2013 |
Patent application number | Description | Published |
20140278266 | SYSTEM AND METHOD FOR MODELING EPITAXIAL GROWTH IN A 3-D VIRTUAL FABRICATION ENVIRONMENT - A virtual fabrication environment for semiconductor device structure development is discussed that enables the use of a selective epitaxy process to virtually model epitaxial growth of a crystalline material layer. The epitaxial growth occurs on a crystalline substrate surface of a virtually fabricated model device structure. A surface growth rate may be defined over possible 3D surface orientations of the virtually fabricated device structure by modeling the growth rates of the three major families of crystal planes. Growth rates along neighboring non-crystalline material may also be modeled. | 09-18-2014 |
20140282302 | Multi-etch process using material-specific behavioral parameters in 3-D virtual fabrication environment - A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior. | 09-18-2014 |
20140282324 | PREDICTIVE 3-D VIRTUAL FABRICATION SYSTEM AND METHOD - A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest. | 09-18-2014 |
20140282328 | DESIGN RULE CHECKS IN 3-D VIRTUAL FABRICATION ENVIRONMENT - A virtual fabrication environment that enables 3D Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) on 3D structural models of semiconductor devices to be performed is discussed. The virtual fabrication environment may perform 3D design rule checks, such as minimum line width, minimum space between features, and minimum contact area between adjacent materials, directly in 3D without making assumptions about the translation from 2D design data to a 3D structure effected by an integrated process flow for semiconductor devices. The required number of 3D design rule checks may therefore be significantly reduced from the number of design rule checks required in 2D environments. Embodiments may also perform the 3D design rule checks for a range of statistical variations in process and design parameters. | 09-18-2014 |
Patent application number | Description | Published |
20080233743 | Method and Structure for Self-Aligned Device Contacts - Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole. | 09-25-2008 |
20080308936 | METHOD AND STURCTURE FOR SELF-ALIGNED DEVICE CONTACTS - Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole. | 12-18-2008 |
20090090974 | DUAL STRESS LINER STRUCTURE HAVING SUBSTANTIALLY PLANAR INTERFACE BETWEEN LINERS AND RELATED METHOD - A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile stress liner over an NFET, the NFET including a PFET adjacent thereto; and a compressive stress liner over the PFET, wherein an upper surface of the compressive stress liner is substantially planar with an upper surface of the tensile stress liner at an interface therebetween. | 04-09-2009 |
20100283089 | METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING - Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer. | 11-11-2010 |
20120086077 | FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE - An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage. | 04-12-2012 |
20120119778 | POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES - A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines. | 05-17-2012 |
20120187490 | FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE - A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate. | 07-26-2012 |
20120305998 | HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY - In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array. | 12-06-2012 |
20130183806 | High Density Memory Cells Using Lateral Epitaxy - In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array. | 07-18-2013 |
Patent application number | Description | Published |
20110067601 | PRODUCTION OF CEMENT ADDITIVES FROM COMBUSTION PRODUCTS OF HYDROCARBON FUELS AND STRENGTH ENHANCING METAL OXIDES - The present invention provides combustion products of hydrocarbon fuels and controlled amounts of metal oxide strength enhancing materials. The combustion products are useful as additives to cementitious materials. A hydrocarbon fuel such as coal is introduced into a combustion chamber and selected amounts of materials comprising CaO, SiO | 03-24-2011 |
20130125791 | IN-PROCESS ADDITION OF PROPERTY-ENHANCING ADDITIVES TO COAL COMBUSTION PRODUCTS USED IN CEMENTICIOUS MATERIALS - In-process systems and methods for treating coal combustion products with property-enhancing additives are disclosed. Coal combustion products such as fly ash are collected upon their formation and are contemporaneously treated with additives such as dispersants, rheology modifiers, retarders and accelerators to improve properties of the treated products when they are used in cement, concrete, mortar and other hydraulic mixtures. | 05-23-2013 |
20130125792 | PRODUCTION OF COAL COMBUSTION PRODUCTS FOR USE IN CEMENTITIOUS MATERIALS - A method and system for producing modified coal combustion products are disclosed. The additives reduce the particle sizes of the coal combustion product and may reduce the amount of un-burned carbon in the coal combustion product, making the modified product useful as an addition to cementitious materials. | 05-23-2013 |
20130125799 | SYSTEMS AND METHODS FOR COMMINUTING AND RECIRCULATING COAL COMBUSTION PRODUCTS - A method and system for reducing the un-burned carbon content in coal combustion products are disclosed. A coal combustion product is separated into a coarse particle fraction and a fine particle fraction, and the coarse particles are comminuted by milling, grinding or the like. Additives may be added of the coarse particles prior to comminution. The comminuted particles are then co-combusted with coal to burn at least a portion of the un-burned carbon contained in the original coal combustion product. | 05-23-2013 |