Patent application number | Description | Published |
20090050973 | INTEGRATED CIRCUIT INCLUDING A FIRST CHANNEL AND A SECOND CHANNEL - An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width. | 02-26-2009 |
20090128383 | Compensation of nonlinearity of single ended Digital to analog converters - This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit. | 05-21-2009 |
20090147542 | Systems and methods for driving a transistor - This disclosure relates to monitoring and controlling a voltage characteristic of a Drain Extended Metal Oxide Semiconductor (DeMOS) transistor. | 06-11-2009 |
20090250763 | INTEGRATED CIRCUIT INCLUDING A FIRST CHANNEL AND A SECOND CHANNEL - An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width. | 10-08-2009 |
20100111222 | Digital Modulation Jitter Compensation for Polar Transmitter - This disclosure relates to clock jitter suppression in digital to analog converter generated pulses for a polar transmitter. | 05-06-2010 |
20100141327 | COMPENSATION OF NONLINEARITY OF SINGLE ENDED DIGITAL TO ANALOG CONVERTERS - This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit. | 06-10-2010 |
20110037499 | COMPARATOR FOR TECHNOLOGIES WITH TRANSIENT VARIATIONS OF TRANSISTOR PARAMETERS - This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors' parameters. | 02-17-2011 |
20110043293 | DeMOS VCO - The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices. | 02-24-2011 |
20110043294 | DeMOS DCO - The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices. | 02-24-2011 |
20110085616 | DIGITAL TO ANALOG CONVERTER COMPRISING MIXER - In some embodiments, digital to analog converters are provided which comprise a plurality of cells. Each cell comprises a mixer and coupling circuitry to selectively couple a local oscillator signal to said mixer. | 04-14-2011 |
20110285453 | COMPENSATION OF NONLINEARITY OF SINGLE ENDED DIGITAL TO ANALOG CONVERTERS - This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit. | 11-24-2011 |
20120170673 | DIGITAL MODULATION JITTER COMPENSATION FOR POLAR TRANSMITTER - This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation. | 07-05-2012 |
20120176258 | Calibration Circuit and Method for Calibrating Capacitive Compensation in Digital-to-Analog Converters - A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor. | 07-12-2012 |
20140146913 | Capacitive Digital to Analog Converter - Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC. | 05-29-2014 |
20140146914 | Digital to Analog Converter Comprising Mixer - One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and a plurality of cells arranged in rows and columns. Each cell includes a current source. A row decoder and a column decoder provide respective control signals to respective rows and respective columns to selectively couple a number of the current sources to an output of the DAC. The number of current sources which are coupled to the output by the control signals is dependent on the multi-bit digital input signal. At least one of the control signals is modulated based on a local oscillator signal. | 05-29-2014 |
20140269976 | Radio Frequency Digital to Analog Converter - A RF digital to analog converter has a first capacitor arrangement, a first common node, and a first controller. The first capacitor arrangement has multiple switchable capacitor paths arranged in parallel. Respective switchable capacitor paths have a switchable element and a capacitor coupled in series. The first common node is connected to the multiple switchable capacitor paths. The first controller receives a baseband signal having an in-phase component and a quadrature component, and a local oscillator (LO) signal having an in-phase LO signal and a quadrature LO signal. The first controller combines the in-phase component and the in-phase LO signal to obtain a first in-phase modulation signal and combines the quadrature component and the quadrature LO signal to obtain a first quadrature modulation signal. The first controller controls the multiple switchable capacitor paths of the first capacitor arrangement with the first in-phase modulation signal and/or the first quadrature modulation signal. | 09-18-2014 |
20140328429 | DIGITAL TO ANALOG CONVERTER COMPRISING MIXER - One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and a plurality of unit cells arranged in rows and columns. A row decoder and a column decoder provide respective control signals to respective rows and respective columns to selectively couple a number of the unit cells to an output of the DAC. The number of unit cells which are coupled to the output by the control signals is dependent on the multi-bit digital input signal. At least one of the control signals is modulated based on a local oscillator signal. | 11-06-2014 |
20140341322 | Radio Frequency Digital to Analog Converter - A RF digital to analog converter has a first capacitor arrangement, a first common node, and a first controller. The first capacitor arrangement has multiple switchable capacitor paths arranged in parallel. Respective switchable capacitor paths have a switchable element and a capacitor coupled in series. The first common node is connected to the multiple switchable capacitor paths. The first controller receives a baseband signal having a component, and a local oscillator (LO) signal. The first controller combines the component and the LO signal to obtain a first modulation signal. The first controller controls the multiple switchable capacitor paths of the first capacitor arrangement with the first modulation signal. | 11-20-2014 |
20140347203 | CAPACITIVE DIGITAL TO ANALOG CONVERTER - Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC. | 11-27-2014 |