Patent application number | Description | Published |
20130154694 | PHASE-LOCKED LOOP FREQUENCY STEPPING - A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division. | 06-20-2013 |
20130154695 | PHASE LOCK LOOP WITH ADAPTIVE LOOP BANDWIDTH - Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors. | 06-20-2013 |
20140029646 | DISABLING SPREAD-SPECTRUM CLOCK SIGNAL GENERATION - A device may generate a clock signal using spread-spectrum clocking. The spread-spectrum clocking may modulate a frequency of the clock signal to produce a plurality of frequencies for the clock signal during a modulation cycle. The device may receive an instruction to disable the spread-spectrum clocking, and may disable the spread spectrum clocking at the end of the modulation cycle. | 01-30-2014 |
20150061737 | PHASE LOCKED LOOP WITH BANDWIDTH CONTROL - A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal. | 03-05-2015 |