Patent application number | Description | Published |
20120022846 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRO-MIGRATION AWARENESS - Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the EM related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools. | 01-26-2012 |
20120023465 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH SIMULATION AWARENESS - Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment. | 01-26-2012 |
20120023467 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRICAL AWARENESS - Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness. | 01-26-2012 |
20120023468 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR CONSTRAINT VERIFICATION FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRICAL AWARENESS - Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met. | 01-26-2012 |
20120023471 | METHOD, APPARATUS, AND ARTICLE OF MANUFACTURE FOR PROVIDING IN SITU, CUSTOMIZABLE INFORMATION IN DESIGNING ELECTRONIC CIRCUITS WITH ELECTRICAL AWARENESS - Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation. | 01-26-2012 |
20120023472 | METHOD, APPARATUS, AND ARTICLE OF MANUFACTURE FOR PROVIDING IN SITU, CUSTOMIZABLE INFORMATION IN DESIGNING ELECTRONIC CIRCUITS WITH ELECTRICAL AWARENESS - Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation. | 01-26-2012 |
20140237440 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH SIMULATION AWARENESS - Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment. | 08-21-2014 |
Patent application number | Description | Published |
20090150854 | Computer Method and Apparatus for Providing Model to Model Transformation Using an MDA Approach - A Model Transformation Authoring Framework (MTAF)method and apparatus for authoring and providing model-to-model transformations from one domain to another domain is disclosed. Given a domain and a target domain, at least the given domain having a respective structured hierarchy, the invention system enables a user to specify a declarative mapping (transformation declarative) between a domain specific language modeling the given domain and a modeling language modeling the target domain. The declarative mapping models how the domain specific language modeling the given domain relates to the modeling language of the target domain. The system generates a transformation code implementation of a transformation from the given domain to the target domain. The MTAF provides to the user design decisions with respect to Specification, Transformation Rules, Rule Organization, Rule Application Control, Source-Target Relationship, Incrementality, and Directionality and Tracing. The generated transformation code is executed at runtime to perform the transformation of the domain specific language of the given domain to the modeling language of the target domain. Instances of models of the target domain resulting from the performed transformation at runtime may be output to other model transformations, to JET templates, or may be persisted, merged or chained among other post processing. | 06-11-2009 |
20090150856 | UML Profile Transformation Authoring Method and System - A method and apparatus for authoring model-to-model transformations of programming models involving profiles is disclosed. Using a declarative mapping between a given profile of a subject programming model and a target profile of a target programming model, transformation of the given profile is specified and results in a declarative specification. Similarly the declarative mapping may be to a profile of a target programming model (without a corresponding source side profile) or from a profile of a source programming model (without a corresponding target side profile). Based on the declarative specification, a transformation code implementation (e.g. a transformation API) is generated. The given profile is specified as an input domain or as an output domain along with a meta model of the subject programming model. The generated transformation code implementation effectively handles complexities of dealing with the given profile at run time. | 06-11-2009 |
20120023477 | Pattern Implementation Technique - A pattern implementation technique in which a pattern is defined as a software artifact that comprises a pattern signature representing one or more parameters of the pattern and a pattern implementation model representing one or more methods for expanding the pattern in a selected software context by assigning one or more arguments to the one or more parameters. | 01-26-2012 |
Patent application number | Description | Published |
20110133259 | STRESSED BARRIER PLUG SLOT CONTACT STRUCTURE FOR TRANSISTOR PERFORMANCE ENHANCEMENT - A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices. | 06-09-2011 |
20110150031 | THERMAL SENSOR USING A VIBRATING MEMS RESONATOR OF A CHIP INTERCONNECT LAYER - Methods and apparatuses for Micro-Electro-Mechanical Systems (MEMS) resonator to monitor temperature in an integrated circuit. Fabricating the resonator in an interconnect layer provides a way to implement thermal detection means which is tolerant of manufacturing process variations. Sensor readout and control circuits can be on silicon if desired, for example, a positive feedback amplifier to form an oscillator in conjunction with the resonator and a counter to count oscillator frequency. | 06-23-2011 |
20120007242 | INTERCONNECTS HAVING SEALING STRUCTURES TO ENABLE SELECTIVE METAL CAPPING LAYERS - Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect. | 01-12-2012 |
20120068273 | STRESSED BARRIER PLUG SLOT CONTACT STRUCTURE FOR TRANSISTOR PERFORMANCE ENHANCEMENT - A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices. | 03-22-2012 |
20130270675 | ON-CHIP CAPACITORS AND METHODS OF ASSEMBLING SAME - An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes. | 10-17-2013 |
20130320564 | AVD HARDMASK FOR DAMASCENE PATTERNING - A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point. | 12-05-2013 |
20140151889 | TECHNIQUES FOR ENHANCING DIELECTRIC BREAKDOWN PERFORMANCE - Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (E | 06-05-2014 |
Patent application number | Description | Published |
20110106808 | MULTI-DIMENSIONAL CONTENT ORGANIZATION AND DELIVERY - The present disclosure provides novel systems and methods for providing multi-dimensional categorization within a multi-tenant database system (“MTS”). Data items in entities stored in a MTS may be categorized along one or more category dimensions. A search query may include one or more selected categories in one or more category dimensions. Categorization methodologies include multi-selection, multi-position, and combinations thereof. Users of the MTS may also be categorized along one or more category dimensions. A filter may present a subset of data items relevant to a user in accordance with their categorization. | 05-05-2011 |
20110225119 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR VERSIONING CONTENT IN A DATABASE SYSTEM USING CONTENT TYPE SPECIFIC OBJECTS - In accordance with embodiments, there are provided mechanisms and methods for versioning content in a database system using content type specific objects. These mechanisms and methods for versioning content in a database system using content type specific objects can enable embodiments to provide a database system which stores information associated with multiple versions of content. The ability of embodiments to provide a database system which supports content versioning can enable an efficient and comprehensive storage of content types having different features by the database system. | 09-15-2011 |
20110276535 | KNOWLEDGE ARTICLE WORKFLOW MANAGEMENT - A computer implemented method a document management workflow in a multi-tenant system environment is disclosed. The method includes receiving instructions to create a composition a document. The document is encapsulated in a knowledge article version and the knowledge article version having a document category. The knowledge article version is associated with a knowledge article. The method further includes invoking the document management workflow that is specific to the knowledge article, the knowledge article version and the document category and configuring the document management workflow to include a plurality of workflow steps based on the knowledge article, the knowledge article version and the document category. Each of the plurality of workflow steps are then associated with one or more triggers and actor roles. The actor roles define permissible actions in each of the plurality of workflow steps. Data in the knowledge article and the knowledge article version are configured to be updated with the movement of a document in the plurality of workflow steps. The document management workflow provides cyclic processing steps with no termination state. | 11-10-2011 |
20120117013 | METHOD AND SYSTEM FOR SELECTING A SYNCHRONOUS OR ASYNCHRONOUS PROCESS TO DETERMINE A FORECAST - In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous; asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations. | 05-10-2012 |
20120117014 | METHOD AND SYSTEM FOR SELECTING A SYNCHRONOUS OR ASYNCHRONOUS PROCESS TO DETERMINE A FORECAST - In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous/asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations. | 05-10-2012 |
20130041718 | METHOD AND SYSTEM FOR SELECTING A SYNCHRONOUS OR ASYNCHRONOUS PROCESS TO DETERMINE A FORECAST - In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous/asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations. | 02-14-2013 |
20130066680 | METHOD AND SYSTEM FOR SELECTING A SYNCHRONOUS OR ASYNCHRONOUS PROCESS TO DETERMINE A FORECAST - In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous/asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations. | 03-14-2013 |
20140324540 | METHOD AND SYSTEM FOR SELECTING A SYNCHRONOUS OR ASYNCHRONOUS PROCESS TO DETERMINE A FORECAST - In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous/asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations. | 10-30-2014 |
20140330617 | Selecting a Synchronous or Asynchronous Process to Determine a Forecast - In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous/asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations. | 11-06-2014 |
Patent application number | Description | Published |
20110276601 | KNOWLEDGE BASE COMPUTER MANAGEMENT NETWORK - The present invention features a computer implemented method and network for managing a knowledge base stored in a multi-tenant architecture. The method includes storing information corresponding to a plurality of KnowledgeArticles amongst a plurality of tables. Information in a first of the plurality of tables includes data corresponding to an online version of said KnowledgeArticles and data related to changes to the KnowledgeArticles. Information contained in a second table comprises a subset of the data that is independent of the data related to the changes. Changes to the KnowledgeArticles are recorded in the second table in response to changes made to the first table. Access to information in the first table is restricted access to users having write access to said KnowledgeArticles. | 11-10-2011 |
20110307510 | Methods and Systems for Analyzing Search Terms in a Multi-Tenant Database System Environment - Knowledge base is gaining popularity as a customer support tool. Customers search the knowledge base for solutions to their issues. Keywords searched in knowledge base are analyzed and reports are made available for managers and supervisors to understand the trends and requirements of customers. The number of keywords searched can be extremely large in some organizations. In this specification, storing the keywords in a meaningful way in order to generate report for further analysis is discussed. Efficient data storage helps in managing voluminous data and also reducing the amount of memory required to store the data. Any of the above embodiments can be used independently or together with any combination of other embodiments. | 12-15-2011 |
20120005537 | IDENTIFYING BUGS IN A DATABASE SYSTEM ENVIRONMENT - A system and method for identifying bugs in a database system. In one embodiment, a method includes running a plurality of tests on a software application, and rerunning one or more tests of the plurality of tests. The method also includes identifying one or more bugs in the one or more tests based on inconsistent test results. | 01-05-2012 |
20120330644 | MULTI-LINGUAL KNOWLEDGE BASE - Mechanisms and methods for enabling customers to manage multi-lingual knowledge bases, so that end users can access articles based on a language the end user chooses, while also providing publishers with tools to manage articles in different languages and to translate them, either using an external vendor or leveraging in house translators, and providing administrators (knowledge managers) with the ability to setup or choose which languages are available in the knowledge base, as well as default language assignments for translations. | 12-27-2012 |
20130151231 | MULTI-LINGUAL KNOWLEDGE BASE - Mechanisms and methods for enabling customers to manage multi-lingual knowledge bases, so that end users can access articles based on a language the end user chooses, while also providing publishers with tools to manage articles in different languages and to translate them, either using an external vendor or leveraging in house translators, and providing administrators (knowledge managers) with the ability to setup or choose which languages are available in the knowledge base, as well as default language assignments for translations. | 06-13-2013 |
20130311225 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR MANAGING BUSINESS HOURS IN AN ON-DEMAND SERVICE - In accordance with embodiments, there are provided mechanisms and methods for managing multiple business hours in anon-demand service. These mechanisms and methods for managing multiple business hours in an on-demand service can enable embodiments to provide access to a stored set of business hours for a user to track, at a user level. The ability of embodiments to provide this access may allow users of such on-demand services better insight as to how much time their agents are spending on cases. | 11-21-2013 |
Patent application number | Description | Published |
20110247872 | DEBOND INTERCONNECT STRUCTURES - The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress. | 10-13-2011 |
20120038379 | PROBES FORMED FROM SEMICONDUCTOR REGION VIAS - Embodiments of the invention describe forming a set of probes using semiconductor regions each including a plurality of vias. A first set of probe segments may be formed from a first set of vias on a first semiconductor region. A second set of probe segments may be formed from a second set of vias on a second semiconductor region and bonded to the first set of probe segments. At least one spring comprising a dielectric material may be formed to couple the first set of probe segments, while a set of metal tips disposed on the second set of probe segments. | 02-16-2012 |
20130000117 | LIQUID METAL INTERCONNECTS - Embodiments of the invention provide methods for forming electrical connections using liquid metals. Electrical connections that employ liquid metals are useful for testing and validation of semiconductor devices. Electrical connections are formed between the probes of a testing interface and the electronic interface of a device under test through a liquid metal region. In embodiments of the invention, liquid metal interconnects are comprised of gallium or liquid metal alloys of gallium. The use of liquid metal contacts does not require a predetermined amount of force be applied in order to reliably make an electrical connection. | 01-03-2013 |
20140029150 | INTERPOSER TO REGULATE CURRENT FOR WAFER TEST TOOLING - An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount. | 01-30-2014 |
20140092574 | INTEGRATED VOLTAGE REGULATORS WITH MAGNETICALLY ENHANCED INDUCTORS - Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate. In further embodiments, integrated circuitry on a same substrate as the magnetically enhanced inductor, or on another substrate stacked thereon, completes the VR and/or is powered by the VR circuitry. | 04-03-2014 |
20140106560 | DEBOND INTERCONNECT STRUCTURES - The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress. | 04-17-2014 |
20140117559 | PROCESS AND MATERIAL FOR PREVENTING DELETERIOUS EXPANSION OF HIGH ASPECT RATIO COPPER FILLED THROUGH SILICON VIAS (TSVS) - Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW | 05-01-2014 |
20150008950 | MANUFACTURING ADVANCED TEST PROBES - Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed. | 01-08-2015 |