Patent application number | Description | Published |
20080244493 | PATTERN BASED ELABORATION OF HIERARCHICAL L3GO DESIGNS - A system, method and program product that utilizes flat pattern based L3GO elaboration in a hierarchical environment to create a nested conventional layout. A system is provide for processing a glyph layout to generate shapes for use in a VLSI (very large scale integrated circuit) design process, including: a hierarchical pattern search system that matches patterns from a pattern library to a set of glyph data, wherein the patterns have dependencies that cross hierarchical design boundaries; and a target shape generation system that selects patterns from a set of matching patterns and generates associated shapes. | 10-02-2008 |
20090204930 | IPHYSICAL DESIGN SYSTEM AND METHOD - A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency. | 08-13-2009 |
20100058265 | Parallel Intrusion Search in Hierarchical VLSI Designs with Substituting Scan Line - Mechanisms are provided for performing intrusion searching of a hierarchical integrated circuit design. These mechanisms may receive the hierarchical integrated circuit design and perform a parallel intrusion search operation, that utilizes a substituting scan line, on the hierarchical integrated circuit design to identify intrusions of geometric objects in the hierarchical integrated circuit design. The mechanisms may further record intrusions of geometric objects in the hierarchical integrated circuit design identified by the parallel intrusion search operation. The parallel intrusion search operation may utilize a plurality of separate intrusion searches executed by the data processing system in parallel on the hierarchical integrated circuit design. | 03-04-2010 |
20110289472 | LAYOUT QUALITY EVALUATION - A method for quantifying and improving layout quality of an IC is disclosed. The method includes receiving a drawn layout and placing essentially one dimensional measurement markers (chords) at various location in the drawn layout. This placement is done in such manner that contours of shapes in the drawn layout intersect a chord in at least two places. The length of the chord is defined as its portion delimited by the intersections, and a measurement of the chord is defined as obtaining its length. The drawn layout is subjected, with the exception of the chords, to a patterning simulation at a selected processing point. Following the simulation the chords are measured and the obtained lengths associated with the drawn layout and the processing point. The patterning simulation may be carried out at a variety processing points and the chord lengths following each simulation are associated with the respective processing point. The sets of lengths obtained at the various processing points are used to quantitatively evaluate the layout quality, to improve the layout quality and tune the processing window. | 11-24-2011 |
20110314238 | COMMON MEMORY PROGRAMMING - A method for unidirectional communication between tasks includes providing a first task having access to an amount of virtual memory, blocking a communication channel portion of said first task's virtual memory, such that the first task cannot access said portion, providing a second task, having access to an amount of virtual memory equivalent to the first task's virtual memory, wherein a communication channel portion of the second task's virtual memory corresponding to the blocked portion of the first task's virtual memory is marked as writable, transferring the communication channel memory of the second task to the first task, and unblocking the communication channel memory of the first task. | 12-22-2011 |
20120167029 | PHYSICAL DESIGN SYSTEM AND METHOD - A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency. | 06-28-2012 |