Ficke

Brian Lon Ficke, La Jolla, CA US

Patent application number	Description	Published
20100123571	INSPECTION SYSTEM AND METHOD - A method includes determining a position of a person within an inspection system, and performing a sensor system scan using a sensor system within the inspection system. The sensor system scan includes detecting an unusual physical characteristic of at least one of the person and an item on the person. The results of the sensor system scan are output.	05-20-2010

Geoff Ficke, Warsaw, KY US

Patent application number	Description	Published
20090084924	DOCUMENT HOLDER FOR CARTS - A document holder is provided for a vehicle such as a cart, and especially a shopping cart having a back panel. The document holder includes a writing portion and a bracket portion. A securing member is provided at the writing portion to secure a piece of paper such as a grocery list or coupons. Preferably, the bracket portion has a forward bracket member spaced from a rearward bracket member to define a channel for receiving an upper portion of the back panel to support the holder. The securing member may be configured to hold a writing instrument. An advertisement holder may be positioned on the holder to hold and protect advertisements, store announcements, pictures, or the like while also providing a writing surface thereon. In a preferred embodiment, a document holder includes a flexible, resilient frame or bumper, and/or a two-piece bracket portion for attachment to a shopping cart.	04-02-2009

Grace Ficke, Chicago, IL US

Patent application number	Description	Published
20150014481	RAIL MOUNTED BEVERAGE DISPENSER FOR COMMERCIAL AIRPLANES - A galley cart is suspended from a rail or track that extends along the length of an aircraft cabin above the aisle and rows of passenger seats of the aircraft. The galley cart is automated to move along the track above the aisle in response to movements of a flight attendant that is serving passengers from the suspended galley cart. The galley cart is provided with open bins for storage of food products, a beverage dispenser that is operable by the flight attendant to dispense a beverage requested by a passenger from a plurality of different beverages available from the suspended cart, and an ice dispenser for serving ice with the beverages requested by the passengers.	01-15-2015

Joel T. Ficke, Bloomer, WI US

Patent application number	Description	Published
20120047481	IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK - A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.	02-23-2012
20120194236	IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK - A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.	08-02-2012
20120212280	IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL - A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.	08-23-2012
20120331432	IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL - A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.	12-27-2012
20130088269	IMPLEMENTING CONTROL VOLTAGE MIRROR - A circuit for implementing a control voltage mirror for phase error and jitter performance optimization and a design structure on which the subject circuit resides are provided. The control voltage mirror is used with a phase locked loop filter utilizing a thin oxide filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier holding voltage across the capacitor to be near or at zero volts, substantially eliminating capacitor leakage current to provide phase error and jitter performance optimization.	04-11-2013
20130106461	IMPLEMENTING SCREENING FOR SINGLE FET COMPARE OF PHYSICALLY UNCLONABLE FUNCTION (PUF)	05-02-2013
20140167213	Moat Construction to Reduce Noise Coupling to a Quiet Supply - A semiconductor chip having a P− substrate and an N+ epitaxial layer grown on the P− substrate is shown. A P− circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat.	06-19-2014

Joel T. Ficke, Blommer, WI US

Patent application number	Description	Published
20110298474	IMPLEMENTING INTEGRAL DYNAMIC VOLTAGE SENSING AND TRIGGER - A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output.	12-08-2011

Joel T. Ficke, Madison, WI US

Patent application number	Description	Published
20110317829	Physically Unclonable Function Implemented Through Threshold Voltage Comparison - Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.	12-29-2011

Joel Thomas Ficke, Madison, WI US

Patent application number	Description	Published
20120133413	DESIGN STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT - The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.	05-31-2012
20120187987	STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT - The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.	07-26-2012

Mark Ficke, New York, NY US

Patent application number	Description	Published
20110238556	SYSTEM FOR MATCHING INTERNAL ORDERS - A processor coupled to a memory may receive a first trading order from a first trading participant associated in the at least one database with a first entity, the first trading order comprising a price. The processor may, after receiving the first trading order, receive a second trading order from a second trading participant associated in the at least one memory with a second entity different from the first entity, the second trading order comprising the price. The processor may ordering the first trading order ahead of the second trading order in a trading order queue at the price. After receiving the first and second trading orders and while the first trading order is available for execution, the processor may receive a third trading order from a third trading participant associated with the second entity in the at least one memory, the third trading order being contra to the first and second trading orders at the same price. The processor may determining that the second and third trading orders are associated with the same entity in the database. The processor may, based at least in part on determining that the second and third trading orders are associated with the same entity, match at least a portion of the second trading order with at least a portion of the third trading order. The processor may cause the at least portion of the second trading order to be executed against the at least portion of the third trading order.	09-29-2011

Nancy Ficke, Warsaw, KY US

Patent application number	Description	Published
20090084924	DOCUMENT HOLDER FOR CARTS - A document holder is provided for a vehicle such as a cart, and especially a shopping cart having a back panel. The document holder includes a writing portion and a bracket portion. A securing member is provided at the writing portion to secure a piece of paper such as a grocery list or coupons. Preferably, the bracket portion has a forward bracket member spaced from a rearward bracket member to define a channel for receiving an upper portion of the back panel to support the holder. The securing member may be configured to hold a writing instrument. An advertisement holder may be positioned on the holder to hold and protect advertisements, store announcements, pictures, or the like while also providing a writing surface thereon. In a preferred embodiment, a document holder includes a flexible, resilient frame or bumper, and/or a two-piece bracket portion for attachment to a shopping cart.	04-02-2009

Steven D. Ficke, Stevensville, MI US

Patent application number	Description	Published
20150013074	LAUNDRY TREATING APPLIANCE WITH REMOTELY CONTROLLED AIRFLOW AND METHOD OF OPERATING THE SAME - The souring of wet laundry in a laundry treating appliance may be retarded by sending an alert signal indicative of an ending of a cycle of operation from the laundry treating appliance to a remote electronic device. The appliance may receive an authorization signal from the electronic device indicative of an instruction to execute an anti-sour cycle. An anti-sour cycle comprising the energizing of a fan to flow air through a laundry treating chamber may be automatically initiated for the laundry treating appliance.	01-15-2015