| Patent application number | Description | Published |
|---|
| 20120262149 | LOOP PARAMETER SENSOR USING REPETITIVE PHASE ERRORS - A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL. | 10-18-2012 |
| 20130057327 | REDUCING PHASE LOCKED LOOP PHASE LOCK TIME - There is provided a method for reducing lock time in a phase locked loop. The method includes detecting a saturation condition on a path within the phase locked loop. The method further includes temporarily applying saturation compensation along the path when the saturation condition is detected. | 03-07-2013 |
| 20140184439 | SCALABLE POLARIMETRIC PHASED ARRAY TRANSCEIVER - A polarimetric transceiver front-end includes two receive paths configured to receive signals from an antenna, each receive path corresponding to a respective polarization. Each front-end includes a variable amplifier and a variable phase shifter; a first transmit path configured to send signals to the antenna, where the transmit path is connected to the variable phase shifter of one of the two receive paths and includes a variable amplifier; and a transmit/receive switch configured to select between the first transmit path and the two receive paths for signals, where the transmit/receive switch includes a quarter-wavelength transmission line that adds a high impedance to the transmit path when the transmit/receive switch is in a receiving state. | 07-03-2014 |
| Patent application number | Description | Published |
|---|
| 20130063192 | PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION - A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter. | 03-14-2013 |
| 20130307588 | PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION - A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter. | 11-21-2013 |
| 20140070855 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 03-13-2014 |
| 20140070856 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 03-13-2014 |
| 20150200676 | PREDICTION BASED DIGITAL CONTROL FOR FRACTIONAL-N PLLS - Methods and systems for phase correction include determining a phase error direction and generating a prediction for the phase error based on a sigma-delta error. It is determined whether the prediction agrees with the determined phase error direction. If the prediction does not agree, a phase correction is adjusted in accordance with the predicted phase error. | 07-16-2015 |
| 20150200677 | REMOVING DETERMINISTIC PHASE ERRORS FROM FRACTIONAL-N PLLS - Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio. | 07-16-2015 |
| 20150244320 | RESONATOR HAVING DISTRIBUTED TRANSCONDUCTANCE ELEMENTS - An apparatus comprises a resonator including a plurality of switched impedances spatially distributed within the resonator and a corresponding plurality of transconductance elements distributed within respective distances among the switched impedances. The resonator has a given desired resonant frequency and a given amplitude of response. Combined pairs of the switched impedances and transconductance elements have respective parasitic resonant frequencies which are higher than the given desired resonant frequency and have respective amplitudes of response which are lower than the given amplitude of response. The apparatus may be a voltage controlled oscillator or an active filter. | 08-27-2015 |
