Patent application number | Description | Published |
20110031633 | AIR CHANNEL INTERCONNECTS FOR 3-D INTEGRATION - A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure. | 02-10-2011 |
20110083786 | ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES - An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded. | 04-14-2011 |
20120043814 | SOLAR CELL AND BATTERY 3D INTEGRATION - An integrated photovoltaic cell and battery device, a method of manufacturing the same and a photovoltaic power system incorporating the integrated photovoltaic cell and battery device. The integrated photovoltaic cell and battery device includes a photovoltaic cell, a battery, and interconnects providing three-dimensional integration of the photovoltaic cell and the battery into an integrated device for capturing and storing solar energy. Also provided is a design structure readable by a machine to simulate, design, or manufacture the above integrated photovoltaic cell and battery device. | 02-23-2012 |
20120268985 | RESONANCE NANOELECTROMECHANICAL SYSTEMS - Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions. | 10-25-2012 |
20120286377 | Nanoelectromechanical Structures Exhibiting Tensile Stress And Techniques For Fabrication Thereof - Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions. | 11-15-2012 |
20120318649 | Silicide Micromechanical Device and Methods to Fabricate Same - A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a silicon layer disposed over an insulating layer that is disposed on a silicon substrate; releasing a portion of the silicon layer from the insulating layer so that it is at least partially suspended over a cavity in the insulating layer; depositing a metal (e.g., Pt) on at least one surface of at least the released portion of the silicon layer and, using a thermal process, fully siliciding at least the released portion of the silicon layer using the deposited metal. The method eliminates silicide-induced stress to the released Si member, as the entire Si member is silicided. Furthermore no conventional wet chemical etch is used after forming the fully silicided material thereby reducing a possibility of causing corrosion of the silicide and an increase in stiction. | 12-20-2012 |
20130020183 | Silicide Micromechanical Device and Methods to Fabricate Same - A miniaturized electro-mechanical switch includes a moveable portion having a contact configured to make, when the switch is actuated, an electrical connection between two stationary points. At least the contact is composed of a fully silicided material. A structure includes a silicon layer formed over an insulator layer and a micromechanical switch formed at least partially within the silicon layer. The micromechanical switch has a conductive structure, and where at least electrically contacting portions of the conductive structure are comprised of fully silicided material. | 01-24-2013 |
20130146948 | MICROMECHANICAL DEVICE AND METHODS TO FABRICATE SAME USING HARD MASK RESISTANT TO STRUCTURE RELEASE ETCH - A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure. | 06-13-2013 |
20130183553 | BATTERY WITH SELF-PROGRAMMING FUSE - A useful lifetime of an energy storage device can be extended by providing a series connection of a battery cell and an self-programming fuse. A plurality of series connections of a battery cell and an self-programming fuse can then be connected in a parallel connection to expand the energy storage capacity of the energy storage device. Each self-programming fuse can be a strip of a metal semiconductor alloy material, which electromigrates when a battery cell is electrically shorted and causes increases in the amount of electrical current therethrough. Thus, each self-programming fuse is a self-programming circuit that opens once the battery cell within the same series connection is shorted. | 07-18-2013 |
20140000712 | NIOBIUM THIN FILM STRESS RELIEVING LAYER FOR THIN-FILM SOLAR CELLS | 01-02-2014 |
20140103422 | STRUCTURE FOR MEMS TRANSISTORS ON FAR BACK END OF LINE - A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level. The MEMS cantilever switch is separated from the gate and the drain by a sacrificial material, which is ultimately removed to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain. | 04-17-2014 |
20140106552 | Method Of Fabricating MEMS Transistors On Far Back End Of Line - A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level. The MEMS cantilever switch is separated from the gate and the drain by a sacrificial material, which is ultimately removed to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain. | 04-17-2014 |
20140117498 | Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process - In one aspect, a memory cell capacitor is provided. The memory cell capacitor includes a silicon wafer; at least one trench in the silicon wafer; a silicide within the trench that serves as a bottom electrode of the memory cell capacitor, wherein a contact resistance between the bottom electrode and the silicon wafer is from about 1×10 | 05-01-2014 |
20140120687 | Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process - In one aspect, a method of fabricating a memory cell capacitor includes the following steps. At least one trench is formed in a silicon wafer. A thin layer of metal is deposited onto the silicon wafer, lining the trench, using a conformal deposition process under conditions sufficient to cause at least a portion of the metal to self-diffuse into portions of the silicon wafer exposed within the trench forming a metal-semiconductor alloy. The metal is removed from the silicon wafer selective to the metal-semiconductor alloy such that the metal-semiconductor alloy remains. The silicon wafer is annealed to react the metal-semiconductor alloy with the silicon wafer to form a silicide, wherein the silicide serves as a bottom electrode of the memory cell capacitor. A dielectric is deposited into the trench covering the bottom electrode. A top electrode is formed in the trench separated from the bottom electrode by the dielectric. | 05-01-2014 |
20140151786 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit. | 06-05-2014 |
20140154851 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Methods for making non-volatile switches include depositing gate material in a recess of a substrate; depositing drain metal in a recess of the gate material; planarizing the gate material, drain metal, and substrate; forming sidewalls by depositing material on the substrate around the gate material; forming a flexible conductive element between the sidewalls to establish a gap between the flexible conductive element and the gate material, such that the gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening a circuit; and forming a source terminal in electrical contact with the flexible conductive element. | 06-05-2014 |
20140203360 | REDUCING CONTACT RESISTANCE BY DIRECT SELF-ASSEMBLING - As stated above, methods of forming a source/drain contact for a transistor are disclosed. In one embodiment, a transistor is formed on a semiconductor-on-insulator (SOI) substrate, which includes a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate. This forming can include forming a gate and a source/drain region. A hardmask can then be formed over the transistor and a self-assembling (DSA) polymer can be directed to cover a portion of the source/drain region. A set of trenches can be formed through the hardmask and into the source/drain region using the DSA polymer as a mask. Then the polymer and the hardmask can be stripped, leaving the trenched source/drain region. | 07-24-2014 |
20140264482 | CARBON-DOPED CAP FOR A RAISED ACTIVE SEMICONDUCTOR REGION - After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors. | 09-18-2014 |
20140312249 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-23-2014 |
20140315316 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-23-2014 |
20140326047 | Techniques for Fabricating Janus Sensors - Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid. | 11-06-2014 |
20140326613 | Techniques for Fabricating Janus Sensors - Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid. | 11-06-2014 |
20140345687 | NIOBIUM THIN FILM STRESS RELIEVING LAYER FOR THIN-FILM SOLAR CELLS - A photovoltaic device includes a thermal stress relieving layer on top of a substrate; a back ohmic contact on the thermal stress relieving layer; and a p-type semiconductor photon absorber layer on the back ohmic contact. The back ohmic contact comprises a metallic compound of the sacrificial back electrode metal layer and the absorber layer, in combination with the thermal stress relieving layer. The thermal stress relieving layer has a substantially similar thermal expansion coefficient with respect to the substrate and the absorber layer and a lower Young's modulus with respect to the sacrificial back electrode metal layer. | 11-27-2014 |
20140353589 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20140353590 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20150014755 | JANUS COMPLEMENTARY MEMS TRANSISTORS AND CIRCUITS - A method of fabricating an electromechanical device includes the following steps. A first and a second back gate are formed over a substrate. An etch stop layer is formed covering the first and second back gates. Electrodes are formed over the first and second back gates, wherein the electrodes include one or more gate, source, and drain electrodes, wherein gaps are present between the source and drain electrodes. One or more Janus components are placed the gaps, each of which includes a first portion having an electrically conductive material and a second portion having an electrically insulating material, and wherein i) the first or second portion of the Janus components placed in a first one of the gaps has a fixed positive surface charge and ii) the first or second portion of the Janus components placed in a second one of the gaps has a fixed negative surface charge. | 01-15-2015 |
20150064897 | PROCESS VARIABILITY TOLERANT HARD MASK FOR REPLACEMENT METAL GATE FINFET DEVICES - Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall. | 03-05-2015 |