Patent application number | Description | Published |
20080269446 | Method for Producing Carboxylate-Rich Copolymers from Monoethylenically Unsaturated Monocarboxylic and Dicarboxylic Acids and Carboxylate-Rich Copolymers Having a Low Neurtralization Degree - Partially neutralized carboxylate-rich copolymers, processes for their preparation and methods of using the same are disclosed, the copolymers comprising: monomers (A), (B), and (C); wherein monomer (A) comprises at least one monoethylenically unsaturated monocarboxylic acid, and is present in an amount of 30% to 79.99% by weight; wherein monomer (B) comprises at least one monoethylenically unsaturated dicarboxylic acid selected from the group consisting of acids corresponding to general formula I, acids corresponding to general formula II, anhydrides thereof, and other hydrolyzable derivatives thereof, and is present in an amount of 20.01% to 70% by weight: | 10-30-2008 |
20120202937 | LOW MOLECULAR WEIGHT PHOSPHORUS-CONTAINING POLYACRYLIC ACIDS AND USE THEREOF AS DISPERSANTS - An aqueous solution of acrylic acid polymers having a total phosphorus content of organically and possibly inorganically bound phosphorus, wherein
| 08-09-2012 |
20140166287 | POLYMER FORMULATIONS IN SOLVENTS WITH A HIGH FLASHPOINT, PROCESSES FOR PRODUCTION THEREOF AND USE THEREOF AS POUR POINT DEPRESSANTS FOR CRUDE OILS, MINERAL OILS OR MINERAL OIL PRODUCTS - Polymer formulations comprising at least two different solvents having a flashpoint ≧60° C., and polymeric compositions obtainable by free-radical polymerization of at least one alkyl (meth)acrylate in the presence of at least one ethylene-vinyl ester copolymer. Multistage process for producing such formulations and the use of such formulations as pour point depressants for crude oils, mineral oils or mineral oil products. | 06-19-2014 |
Patent application number | Description | Published |
20080308870 | INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE - An integrated circuit is disclosed. One embodiment provides a field-effect transistor including a gate electrode, a channel region and a first source/drain region. The gate electrode may include a main section determining a first flat band voltage between the gate electrode and the channel region and a first lateral section that is in contact with the main section and that determines a second flat band voltage between the gate electrode and the first source/drain region. The first and second flat band voltages differ by at least 0.1 eV. | 12-18-2008 |
20100025826 | Field Effect Transistors with Channels Oriented to Different Crystal Planes - An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface. | 02-04-2010 |
20130280883 | METHODS OF FORMING BULK FINFET DEVICES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS - Disclosed are methods of forming bulk FinFET semiconductor devices to reduce punch through leakage currents. One example includes forming a plurality of trenches in a semiconducting substrate to define a plurality of spaced-apart fins, forming a doped layer of insulating material in the trenches, wherein an exposed portion of each of the fins extends above an upper surface of the doped layer of insulating material while a covered portion of each of the fins is positioned below the upper surface of the doped layer of insulating material, and performing a process operation to heat at least the doped layer of insulating material to cause a dopant material in the doped layer to migrate from the doped layer of insulating material into the covered portions of the fins and thereby define a doped region in the covered portions of the fins that is positioned under the exposed portions of the fins. | 10-24-2013 |
20140151816 | NOVEL CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME - One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region. | 06-05-2014 |
20140159125 | CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME - One device herein includes first and second spaced-apart active regions, a transistor formed in and above the first active region, wherein the transistor has a gate electrode, a conductive contact landing pad that is coupled to the second active region, wherein the contact landing pad is made of the same conductive material as the gate electrode, and a contact that is coupled to the contact landing pad. One method herein includes forming first and second spaced-apart active regions, forming a layer of gate insulation material on the active regions, performing an etching process to remove the gate insulation material formed on the second active region, performing a common process operation to form a gate electrode structure above the gate insulation material on the first active region and the contact landing pad that is conductively coupled to the second active region and forming a contact to the contact landing pad. | 06-12-2014 |
20140167119 | METHODS OF FORMING A SIDEWALL SPACER HAVING A GENERALLY TRIANGULAR SHAPE AND A SEMICONDUCTOR DEVICE HAVING SUCH A SPACER - A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure. | 06-19-2014 |
20140335668 | CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME - A method of forming a conductive contact landing pad and a transistor includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, and performing an etching process to remove the layer of gate insulation material formed on the second active region so as to thereby expose the second active region. The method further includes performing a common process operation to form a gate electrode structure above the layer of gate insulation material on the first active region for the transistor and the conductive contact landing pad that is conductively coupled to the second active region, and forming a contact to the conductive contact landing pad. | 11-13-2014 |
20150035063 | REDUCED SPACER THICKNESS IN SEMICONDUCTOR DEVICE FABRICATION - In aspects of the present disclosure, a reliable encapsulation of a gate dielectric is provided at very early stages during fabrication. In other aspects, a semiconductor device is provided wherein a reliable encapsulation of a gate dielectric material is maintained, the reliable encapsulation being present at early stages during fabrication. In embodiments, a semiconductor device having a plurality of gate structures is provided over a surface of a semiconductor substrate. Sidewall spacers are formed over the surface and adjacent to each of the plurality of gate structures, wherein the sidewall spacers cover sidewall surfaces of each of the plurality of gate structures. After performing an implantation sequence into the sidewall spacers using adjacent gate structures as implantations masks, shadowing lower portions of the sidewall spacers, an etching process is performed for removing implanted portions from the sidewall spacers, leaving lower shadowed portions of the sidewall spacer as shaped sidewall spacers. | 02-05-2015 |
20150041910 | INTEGRATED CIRCUITS WITH A PARTIALLY-DEPLETED REGION FORMED OVER A BULK SILICON SUBSTRATE AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions. | 02-12-2015 |