Patent application number | Description | Published |
20120262814 | Systems and Methods for Data Processing - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a data decoder circuit, and a multi-path circuit. The data detector circuit is operable to apply a data detection algorithm to a data input and a decoder output to yield a detected output. The data decoder circuit is operable to apply a decoding algorithm to a decoder input to yield the decoder output and a status input. The multi-path circuit is operable to provide the decoder input based at least in part on the detected output and the status input. | 10-18-2012 |
20120266055 | Systems and Methods for Short Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. As an example, a data processing circuit is disclosed that includes a defect detector circuit and a comparator circuit. The defect detector circuit is operable to calculate a correlation value combining at least three of a data input derived from a medium, a detector extrinsic output, a detector intrinsic output and a decoder output. The comparator circuit is operable to compare the correlation value to a threshold value and to assert a media defect indicator when the correlation value is less than the threshold value. | 10-18-2012 |
20130047053 | Systems and Methods for Noise Injection Driven Parameter Selection - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise injection circuit. The noise injection circuit is operable to: determine a difference between a first data output and a second data output to yield an error; and augment an interim data with a noise value corresponding to the error to yield a noise injected output. The interim data may be either the first data output or the second data output. | 02-21-2013 |
20130054664 | Systems and Methods for Anti-Causal Noise Predictive Filtering in a Data Channel - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit. | 02-28-2013 |
20130063835 | Systems and Methods for Generating Predictable Degradation Bias - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit and a bias calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a first series of soft decision data, and to apply the data detection algorithm to a second data set to yield a second series of soft decision data. The bias calculation circuit operable to calculate a series of bias values based at least in part on the first series of soft decision data and the second series of soft decision data. The series of bias values correspond to a conversion between the first series of soft decision data and the second series of soft decision data. | 03-14-2013 |
20130067247 | Systems and Methods for Governing Power Usage in an Iterative Decoding System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a data decoder circuit, and a gating circuit. | 03-14-2013 |
20130067297 | Systems and Methods for Non-Binary Decoding Biasing Control - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols. | 03-14-2013 |
20130111289 | SYSTEMS AND METHODS FOR DUAL PROCESS DATA DECODING | 05-02-2013 |
20130111290 | Systems and Methods for Ambiguity Based Decode Algorithm Modification | 05-02-2013 |
20130111297 | Systems and Methods for Symbol Selective Scaling in a Data Processing Circuit | 05-02-2013 |
20130111309 | Systems and Methods for Selective Decode Algorithm Modification | 05-02-2013 |
20130145238 | ENCODING AND DECODING IN FLASH MEMORIES USING CONVOLUTIONAL-TYPE LOW PARITY DENSITY CHECK CODES - Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline. | 06-06-2013 |
20130159634 | Systems and Methods for Handling Out of Order Reporting in a Storage Device - Various embodiments of the present invention provide systems and methods for handling out of order reporting in a storage device. | 06-20-2013 |
20130173932 | Systems and Methods for Decimation Based Over-Current Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active. | 07-04-2013 |
20130198554 | Systems and Methods for Idle Clock Insertion Based Power Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 08-01-2013 |
20130198584 | Systems and Methods for Multi-Pass Alternate Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, data decoding systems are disclosed that include a data decoder circuit and a decode value modification circuit. | 08-01-2013 |
20130205146 | Systems and Methods for Power Governance in a Data Processing Circuit - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 08-08-2013 |
20130208377 | Systems and Methods for Adaptive Decoder Message Scaling - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for adaptively modifying a scaling factor in a data processing system. | 08-15-2013 |
20130219233 | Systems and Methods for Quality Based Priority Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 08-22-2013 |
20130232155 | Systems and Methods for Out of Order Data Reporting - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for out of order reporting of results from data processing. | 09-05-2013 |
20130232390 | Systems and Methods for Multi-Matrix Data Processing - The present inventions are related to systems and methods for data processing. As one example, a data processing system is discussed that includes a data decoder circuit and a matrix select control circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input using a selected parity check matrix to yield a decoder output. The matrix select control circuit operable to select one of a first parity check matrix and a second parity check matrix as the selected parity check matrix. | 09-05-2013 |
20130246877 | Systems and Methods for Compression Driven Variable Rate Decoding in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. | 09-19-2013 |
20130246888 | Systems and Methods for Out of Order Processing in a Data Retry - Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order. | 09-19-2013 |
20130254619 | Systems and Methods for Mis-Correction Correction in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for mis-correction detection and correction in a data processing system. | 09-26-2013 |
20130254623 | Systems and Methods for Variable Redundancy Data Protection - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system. | 09-26-2013 |
20130262788 | Systems and Methods for External Priority Controlled Data Transfer - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. As an example a system is discussed that includes a data transfer controller circuit operable to provide a read request to a storage device. The read request indicates a data set to be provided from the storage device and a processing priority of at least a portion of the data set. | 10-03-2013 |
20130263147 | Systems and Methods for Speculative Read Based Data Processing Priority - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 10-03-2013 |
20130290798 | Systems and Methods for Short Media Defect Detection Using Non-Binary Coded Information - Various embodiments of the present invention provide systems and methods for media defect detection. | 10-31-2013 |
20130290806 | Systems and Methods for Data Decoder State Preservation During Extended Delay Processing - The present invention is related to systems and methods for maintaining additional processing information during extended delay processing. | 10-31-2013 |
20130297983 | Data Processing System with Failure Recovery - Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors. | 11-07-2013 |
20130308221 | Systems and Methods for Symbol Re-Grouping Decoding Processing - The present invention is related to systems and methods for applying a data decode algorithm to different rotations or modifications of a decoder input as part of data processing. | 11-21-2013 |
20130311845 | SYSTEMS AND METHODS FOR NON-BINARY LDPC ENCODING - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding. | 11-21-2013 |
20130322578 | Systems and Methods for Data Processing Including EET Feedback - The present invention is related to systems and methods for data processing system characterization. | 12-05-2013 |
20130326316 | Systems and Methods for Improved Data Detection Processing - The present invention is related to systems and methods for enhancing data detection in a data processing system. | 12-05-2013 |
20130339827 | Adaptive Calibration of Noise Predictive Finite Impulse Response Filter - Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold. | 12-19-2013 |
20130343495 | APPARATUS AND METHOD FOR BREAKING TRAPPING SETS - An error correction data processing apparatus includes a noise predictive calibration circuit operable to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set, and includes a first noise predictive detector operable to receive the first set of filter coefficients. The apparatus further includes a decoder operable to perform a first global iteration with the first noise predictive detector and determine a violation check count value, and a second noise predictive detector operable to receive the second set of filter coefficients if the violation check count value is less than a predetermined value or receive the first set of filter coefficients if the violation check count value is greater than the predetermined value. | 12-26-2013 |
20130346824 | DYNAMICALLY CONTROLLING THE NUMBER OF LOCAL ITERATIONS IN AN ITERATIVE DECODER - An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is on the path to encountering a trapping set or converging on a valid codeword, a model is generated based on observed numbers of unsatisfied check nodes for a specified number of local iterations. For local iterations following the specified number of local iterations, the observed numbers of unsatisfied check nodes are then compared to the model to determine whether to continue or terminate local iterations of error-correction decoding. | 12-26-2013 |
20140006878 | Systems and Methods for Enhanced Accuracy NPML Calibration | 01-02-2014 |
20140006894 | Systems and Methods for Enhanced Bit Correlation Usage | 01-02-2014 |
20140006905 | Systems and Methods for Multi-Stage Decoding Processing | 01-02-2014 |
20140016220 | Systems and Methods for Hardware Assisted Write Pre-Compensation Enhancement - Various embodiments of the present invention provide systems and methods for calibrating write pre-compensation values. | 01-16-2014 |
20140025904 | Systems and Methods for Gate Aware Iterative Data Processing - The present invention is related to systems and methods for iterative data processing scheduling. | 01-23-2014 |
20140026004 | Systems and Methods for Defect Scanning - The present invention is related to systems and methods for defect scanning. | 01-23-2014 |
20140032454 | Systems and Methods for Data Processing Using Soft Data Shaping - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for manipulating soft data in a data processing system. | 01-30-2014 |
20140032982 | Systems and Methods for Enhanced Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. | 01-30-2014 |
20140032989 | Symbol Selective Scaling With Parity Forcing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing. | 01-30-2014 |
20140032998 | Systems and Methods for Improved Short Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. | 01-30-2014 |
20140032999 | Systems and Methods for Information Divergence Based Data Processing - The present inventions are related to systems and methods for information divergence based data processing. | 01-30-2014 |
20140033001 | Quality Based Priority Data Processing With Soft Guaranteed Iteration - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing with soft guaranteed global processing iterations. | 01-30-2014 |
20140035692 | OPTIMIZED MULTI-LEVEL FINITE STATE MACHINE WITH REDUNDANT DC NODES - A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ML-FSM) having a periodic structure, the periodic structure being defined by a predetermined number of time frames. The ML-FSM may include a plurality of penalty-free edges for connecting nodes in one time frame to nodes at the same level in a subsequent time frame and a plurality of penalty edges for connecting nodes in one time frame to nodes at an upper level in the subsequent time frame. The method may further include utilizing the ML-FSM based modulation coding to facilitate data transmission over the communications channel. | 02-06-2014 |
20140040682 | METHOD AND SYSTEM FOR SYMBOL ERROR RATE ESTIMATION AND SECTOR QUALITY MEASUREMENT - A probabilistic approach of symbol error estimation is disclosed. The probabilistic approach of symbol error estimation reflects the number of symbol errors more precisely than the number of unsatisfied checks. The more precise quality metric calculated in accordance with the present disclosure allows a codec system to achieve a better overall performance. In addition, many other features that previously depend on the number of unsatisfied checks as the sector quality metric may also benefit by adopting the more precise quality metric. | 02-06-2014 |
20140050023 | MEMORY DEVICE HAVING COLLABORATIVE FILTERING TO REDUCE NOISE - An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal. | 02-20-2014 |
20140052893 | FILE DELETION FOR NON-VOLATILE MEMORY - A device includes non-volatile memory and a controller. The controller receives a write request including data and a logical address associated with a file. The controller stores the data at a data storage segment having a physical address and associates the physical address with the logical address and a file identifier for the file. The controller receives a second write request including data and the logical address associated with the file. The controller stores the data at a second data storage segment having a second physical address and associates the second physical address with the logical address and the file identifier. When a file delete request for the file is received, the controller identifies the first physical address and the second physical address using the file identifier and erases the information stored at the first data storage segment and the second data storage segment based upon the file identification. | 02-20-2014 |
20140053037 | Multi-Level LDPC Layered Decoder With Out-Of-Order Processing - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding with out-of-order processing. | 02-20-2014 |
20140055882 | REAL TIME CLOSE LOOP FLY HEIGHT CONTROL - A device includes a disk drive assembly configured to store information using a platter comprising a magnetic material surface and a magnetic head disposed above the magnetic material surface. The magnetic head is configured to move across tracks formed on the platter to write information to the magnetic material surface and read information from the magnetic material surface. The device also includes a controller operatively coupled with the disk drive assembly. The controller is configured to dynamically adjust the height of the magnetic head above the magnetic material surface at each of the tracks by determining a harmonic ratio for a particular track and comparing the harmonic ratio to a reference harmonic ratio for the track. For example, the controller calculates a difference between the harmonic ratio and the reference harmonic ratio. | 02-27-2014 |
20140056067 | THRESHOLD OPTIMIZATION FOR FLASH MEMORY - Described embodiments provide enhanced read accuracy of a multi-level cell (MLC) flash memory. A read request for desired cells is received by a media controller of the memory. The media controller sets m thresholds to initial values, each threshold corresponding to a cell voltage level of the memory, and measures the cell voltage level of a given cell. For each of the desired cells of the memory, the media controller iteratively, until the measured cell voltage level converges on one of the thresholds, compares the measured cell voltage level to the thresholds. If the measured cell voltage level does not converge on one of the thresholds, the media controller updates the thresholds, remeasures the cell voltage level and compares the remeasured cell voltage level to the updated thresholds. Once the measured cell voltage level converges on a threshold, the media controller determines a binary level of the cell. | 02-27-2014 |
20140059377 | DYNAMIC Y-BUFFER SIZE ADJUSTMENT FOR RETAINED SECTOR REPROCESSING - Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system. | 02-27-2014 |
20140063636 | Systems and Methods for Conditional Positive Feedback Data Decoding - The present inventions are related to systems and methods for information data processing included selective decoder message determination. | 03-06-2014 |
20140068367 | LDPC Decoder Trapping Set Identification - The present inventions are related to systems and methods for detecting trapping sets in LDPC decoders, and particularly for detecting variable nodes in trapping sets in a non-erasure channel LDPC decoder. | 03-06-2014 |
20140068368 | LDPC Decoder With Fractional Unsatisfied Check Quality Metric - The present inventions are related to systems and methods for calculating data quality metrics for an LDPC decoder, and particularly for calculating a fractional unsatisfied check quality metric. | 03-06-2014 |
20140068372 | Systems and Methods for Local Iteration Randomization in a Data Decoder - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for local iteration randomization in a data decoder circuit. | 03-06-2014 |
20140068381 | LDPC Decoder Irregular Decoding of Regular Codes - The present inventions are related to systems and methods for irregular decoding of regular codes in an LDPC decoder, and in particular to allocating decoding resources based in part on data quality. | 03-06-2014 |
20140068394 | SYSTEMS AND METHODS FOR SECTOR QUALITY DETERMINATION IN A DATA PROCESSING SYSTEM - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination. | 03-06-2014 |
20140068395 | Systems and Methods for Selectable Positive Feedback Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing. | 03-06-2014 |
20140075264 | CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING - A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword. | 03-13-2014 |
20140078608 | Systems and Methods for Hard Decision Based ITI Cancellation - Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for reducing inter-track interference in relation to processing data retrieved from a storage medium. | 03-20-2014 |
20140082448 | LDPC Decoder With Dynamic Graph Modification - The present inventions are related to systems and methods for an LDPC decoder with dynamic Tanner graph modification, and in particular, to a non-erasure channel LDPC decoder that implements a probabilistic approach to Tanner graph modification. | 03-20-2014 |
20140082449 | LDPC Decoder With Variable Node Hardening - The present inventions are related to systems and methods for an LDPC decoder with variable node hardening, and in particular, to an LDPC decoder that temporarily hardens the value of a variable node by using check node to variable node (C2V) messages from a previous iteration that are likely to be correct when generating variable node to check node (V2C) messages. | 03-20-2014 |
20140082461 | Systems and Methods for Detector Side Trapping Set Mitigation - Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system. | 03-20-2014 |
20140085743 | REAL TIME MRA ESTIMATION AND CORRECTION USING ADC SAMPLES - Methods and systems for estimating MRA for a hard disk drive are described. The methods and systems described herein provide for real time estimating and correcting magneto-resistive head asymmetry (MRA) in a hard disk drive using analog-to-digital convertor (ADC) samples or counts. Generally, ADC outputs may be obtained by injecting MRA at known values, where an estimated MRA may be derived in real time by applying an equation using particular ADC output values. Once an estimated MRA is obtained, MRA correction may be performed when the estimated MRA is larger than a threshold value, such as by adjusting a channel MRA compensation coefficient. | 03-27-2014 |
20140089767 | METHOD AND SYSTEM FOR GENERATION OF A TIE-BREAKING METRIC IN A LOW-DENSITY PARITY CHECK DATA ENCODING SYSTEM - The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol. | 03-27-2014 |
20140095954 | MODIFIED TARGETED SYMBOL FLIPPING FOR NON-BINARY LDPC CODES - A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set. | 04-03-2014 |
20140095961 | LAYERED DECODER ENHANCEMENT FOR RETAINED SECTOR REPROCESSING - A system is described for recovering data from a number of sectors, such as the sectors of a hard disk drive (HDD) disk platter, and so forth. The system receives data from the sectors via a read channel and uses a layered data decoder to recover data from the sectors. A memory is coupled with the processor and configured to retain data received from one or more of the sectors, e.g., in retained sector reprocessing (RSR) embodiments. The system is configured to update messages in different circulant layers of the data decoder's parity-check matrix. The system uses one message update order in a processing iteration, and different message update orders in subsequent reprocessing iterations. In some embodiments, layer reordering is used for RSR. In some embodiments, circulant reordering is used for RSR. | 04-03-2014 |
20140095963 | PATTERN-DEPENDENT SHORT MEDIA DEFECT DETECTION - Systems and methods for computing sign disagreement between Le and La signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector. | 04-03-2014 |
20140101483 | Systems and Methods for Modified Quality Based Priority Scheduling During Iterative Data Processing - Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 04-10-2014 |
20140101509 | Systems and Methods for Parallel Retry Processing During Iterative Data Processing - Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 04-10-2014 |
20140104720 | ENHANCED QUALITY-SORTING SCHEDULER - Aspects of the disclosure pertain to a read channel system and method for providing sector prioritization for promoting improved sector processing performance. The system and method, during processing of sectors of data, prioritize each of the sectors for further processing based upon: a global iteration index of each sector, trapping set characteristics of each sector and processing latency of each sector. | 04-17-2014 |
20140108875 | Systems and Methods for Indirect Information Assisted Media Defect Scan - Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for media defect detection. | 04-17-2014 |
20140108880 | Systems and Methods for Enhanced Local Iteration Randomization in a Data Decoder - systems and methods for data processing particularly related local iteration randomization in a data decoding circuit. | 04-17-2014 |
20140111880 | MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE FOR MAGNETIC RECORDING CHANNEL - A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure. | 04-24-2014 |
20140115381 | MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE WITH MULTI-PENALTY - Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period. | 04-24-2014 |
20140115407 | Systems and Methods for Short Media Defect Detection Using Multi-Iteration Soft Data Feedback - Various systems and methods for media defect detection. | 04-24-2014 |
20140115430 | Systems and Methods for Iterative Data Processing Using Negative Feedback Iteration - Systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing. | 04-24-2014 |
20140115431 | Systems and Methods for Positive Feedback Short Media Defect Detection - Various systems and methods for media defect detection. | 04-24-2014 |
20140119113 | Threshold Acquisition and Adaption in NAND Flash Memory - A method, apparatus, and controller for acquiring and tracking at least one threshold voltage of at least one cell of at least one flash chip. The method can include acquiring the at least one threshold voltage of a particular cell of the at least one flash cell. The method can further include performing at least one threshold voltage adjustment iteration. | 05-01-2014 |
20140122923 | Sector Failure Prediction Method and Related System - A method and system is disclosed for identification and removal of a memory sector prone to failure. The method performs satisfaction checks on the memory sector and monitors and stores returned Unsatisfied Checks (USC) for analysis by a pattern recognition algorithm. Once a first global iteration is pattern matched with a second global iteration from the sector, the method determines the period of the repetitive pattern. The method then identifies, as the sector prone to failure, the sector having the defined pattern and period. Once identified, the method uses a power management scheme to remove the sector prone to failure from further use by the memory system and displays to a user the details of the action taken. | 05-01-2014 |
20140122959 | Load Balanced Decoding of Low-Density Parity-Check Codes - A method for determining update candidates in a low-density parity-check decoding process includes dividing the quasi-cyclic columns into groups and identifying an update candidate in each group. One or more of the identified update candidates are then updated. | 05-01-2014 |
20140143628 | Low Density Parity Check Decoder With Flexible Saturation - Embodiments of the present inventions are related to systems and methods for decoding data in an LDPC decoder with flexible saturation levels for variable node probability values. | 05-22-2014 |
20140164866 | Low Density Parity Check Decoder With Miscorrection Handling - A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected. | 06-12-2014 |
20140173385 | Low Density Parity Check Decoder With Dynamic Scaling - A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder. | 06-19-2014 |
20140181570 | SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS - An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate. | 06-26-2014 |
20140208180 | Systems and Methods for Reusing a Layered Decoder to Yield a Non-Layered Result - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. | 07-24-2014 |
20140211337 | Systems and Methods for Improved Short Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. | 07-31-2014 |
20140233129 | NOISE PREDICTIVE FILTER ADAPTATION FOR INTER-TRACK INTERFERENCE CANCELLATION - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for adapting noise predictive filters for inter-track interference cancellation in a data processing system. | 08-21-2014 |
20140237313 | Systems and Methods for Trapping Set Disruption - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including utilization of different scaling values on a portion by portion basis during the data decoding. | 08-21-2014 |
20140237314 | Systems and Methods for Skip Layer Data Decoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process. | 08-21-2014 |
20140247514 | Systems and Methods for ADC Sample Based Inter-track Interference Compensation - Various embodiments of the present invention provide systems and methods for mitigating inter-track interference using pre-equalized data samples. | 09-04-2014 |
20140250352 | Systems and Methods for Signal Reduction Based Data Processor Marginalization - Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability, and/or operational improvement capability. | 09-04-2014 |
20140268401 | Systems and Methods for P-Distance Based Priority Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 09-18-2014 |
20140281787 | Min-Sum Based Hybrid Non-Binary Low Density Parity Check Decoder - Systems, methods, devices, circuits for a min-sum based hybrid non-binary low density parity check decoder. | 09-18-2014 |
20140289582 | Systems and Methods for Reduced Constraint Code Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. | 09-25-2014 |
20140313610 | Systems and Methods Selective Complexity Data Decoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including selective complexity data decoding. | 10-23-2014 |
20140334281 | Systems and Methods for Data Processor Marginalization Based Upon Bit Error Rate - Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability, and/or operational improvement capability. | 11-13-2014 |
20140351668 | Systems and Methods for Inter-cell Interference Mitigation in a Flash Memory - The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. | 11-27-2014 |
20140359393 | Systems and Methods for Data Processing Using Global Iteration Result Reuse - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for use of a detector output by a data decoder. | 12-04-2014 |
20140372828 | Systems and Methods for Hybrid Layer Data Decoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. | 12-18-2014 |
20140372836 | Systems and Methods for Data Processing Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data encoding. | 12-18-2014 |
20150039978 | Systems and Methods for Hybrid Priority Based Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 02-05-2015 |
20150089330 | Systems and Methods for Enhanced Data Recovery in a Solid State Memory System - Systems and method relating generally to data processing, and more particularly to systems and methods for recovering data from a solid state memory. | 03-26-2015 |