Patent application number | Description | Published |
20090108393 | Semiconductor Device With a Plurality of Ground Planes - A multi-chip module (MCM) with a plurality of ground planes/layers is provided. Each integrated circuit (IC) chip of the MCM has its own ground plane on a substrate in the MCM. This MCM structure may facilitate separate testing of each IC chip without affecting other chips and without being affected by other chips. This MCM structure also may facilitate testing of interconnects/connections between two or more chips. | 04-30-2009 |
20090257296 | Programmable memory repair scheme - The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element. | 10-15-2009 |
20110016352 | PROGRAMMABLE MEMORY REPAIR SCHEME - The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element. | 01-20-2011 |
20130194854 | MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES - A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. | 08-01-2013 |
20130283110 | CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE - A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element. | 10-24-2013 |
20140247678 | PROGRAMMABLE MEMORY REPAIR SCHEME - A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element. | 09-04-2014 |
20150332746 | MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES - A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. | 11-19-2015 |
20150371722 | CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE - A controller includes a memory test logic circuit to detect a malfunctioning row of primary data storage elements within an external memory device, an internal memory to store an address corresponding to the malfunctioning row of the external memory device, and a memory setup logic circuit to initiate a repair mode in the external memory device and to end the repair mode in the external memory device. The controller further includes a port to couple to an address line to transmit the address corresponding to the malfunctioning row of the external memory device. | 12-24-2015 |