Patent application number | Description | Published |
20080219134 | Method for Positioning a Scanning Probe on a Target Track of a Multi-Track Storage Medium, Storage Device, Scanning Device, and Storage Medium - A method for settling on a target track of a servo system in a storage device ( | 09-11-2008 |
20080225677 | Storage device having flexible architecture and free scalability - A storage device according to the invention has flexible architecture and free scalability. It includes an address input and a data input. It also includes an address and data evaluation unit, which is formed in such a way that it controls a controllable switching means, wherein in operation the address and data evaluation unit depends on the signals of said address and data inputs. Finally, a read/write line for a read/write signal is provided, which can be applied to a local probe data storage unit via the controllable switching means. | 09-18-2008 |
20080235556 | REVERSE CONCATENATION FOR PRODUCT CODES - A system is provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media. | 09-25-2008 |
20080235562 | REVERSE CONCATENATION FOR PRODUCT CODES - Method and computer program product are provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media. | 09-25-2008 |
20080247300 | STORAGE DEVICE AND METHOD FOR SCANNING A STORAGE MEDIUM - A storage device and a method for scanning a storage medium. A storage medium for storing data in the form of marks is scanned by an array of probes for mark detecting purposes in a scanning mode. The storage medium has fields with each field to be scanned by an associated one of the probes. At least one of the fields has marks representing operational data for operating the scanning mode. Scanning parameters are computed from the operational data and the scanning mode is adjusted according to the computed parameters. | 10-09-2008 |
20080253012 | MAGNETIC TAPE READ CHANNEL SIGNAL VALUES DEVELOPED EMPLOYING INTERMEDIATE BITS OF THE PATH MEMORY OF A PRML VITERBI DETECTOR - Magnetic tape read channel signal values are developed employing intermediate bits of the path memory of a PRML Viterbi detector. Identification logic identifies a most likely path memory state of the PRML Viterbi detector from the path metrics of the PRML Viterbi detector. An intermediate bit sequence of the identified most likely path memory state is obtained, the intermediate bit sequence extending from an initiation point of the path memory which is intermediate the output and the input of the PRML Viterbi detector. A sample value is determined which corresponds to the obtained intermediate bit sequence. | 10-16-2008 |
20080256422 | Apparatus for Providing Error Correction Capability to Longitudinal Position Data - A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits for each of the LPOS words. A determination is then made as to whether or not there is an error within one of the LPOS words based on its corresponding syndrome bits. | 10-16-2008 |
20080256423 | Apparatus for Providing Error Correction Capability to Longitudinal Position Data - A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits for each of the LPOS words. A determination is then made as to whether or not there is an error within one of the LPOS words based on its corresponding syndrome bits. | 10-16-2008 |
20080259484 | READ CHANNEL APPARATUS FOR ASYNCHRONOUS SAMPLING AND SYNCHRONOUS EQUALIZATION - A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module. | 10-23-2008 |
20080284365 | SERVO SYSTEM FOR A TWO-DIMENSIONAL MICRO-ELECTROMECHANICAL SYSTEM (MEMS)-BASED SCANNER AND METHOD THEREFOR - A servo control system micro-electromechanical systems (MEMS)-based motion control system (and method therefor), includes a motion generator having an inherent stiffness component. | 11-20-2008 |
20080284624 | HIGH-RATE RLL ENCODING - An unencoded m-bit data input sequence is divided into a block of n bits and a block of m−n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D | 11-20-2008 |
20080297937 | USING A MEASURED ERROR TO DETERMINE COEFFICIENTS TO PROVIDE TO AN EQUALIZER TO USE TO EQUALIZE AN INPUT SIGNAL - Provided are a read channel, storage drive and method using a measured error to determine coefficients to provide to an equalizer to use to equalize an input signal. A read channel is incorporated in a storage device to process signals read from a storage medium. An equalizer uses coefficients to equalize input read signals to produce equalizer output signals. A detector processes adjusted equalizer output signals to determine output values comprising data represented by the input read signals. An equalizer adaptor is enabled to provide a reference measured error and coefficients used to produce the adjusted equalizer signals that are associated with the reference measured error. The equalizer adaptor computes new equalizer coefficients to use to equalize input read signals that result in a new measured error from the detector and computes a new measured error for the new equalizer coefficients. The equalizer adaptor determines whether the new measured error is degraded with respect to the reference measured error and saves the new equalizer coefficients and the new measured error in response to determining that the new measured error is not degraded with respect to the reference measured error. The equalizer adaptor provides the equalizer coefficients associated with the reference measured error to the equalizer to use to equalize input read signals in response to determining that the new measured error is degraded with respect to the reference measured error. | 12-04-2008 |
20080304379 | Writing and Reading of Data in Probe-Based Data Storage Devices - Methods and apparatus are provided for controlling writing and reading of data in an array of A storage fields of a probe-based data storage device in which data is written to and read from the array of storage fields by a corresponding array of probes. One method uses the concept of sub-arrays to provide variable-rate read/write operation. Input data blocks are received for writing to the A-field array, each input data block being writable in A/k | 12-11-2008 |
20080316905 | Data Storage Device - A storage device including a storage medium for storing data in the form of topographic or magnetic marks. At least one probe is mounted on a common frame, the common frame and the storage medium designed for moving relative to each other for creating or detecting said marks. Each probe includes a tip facing the storage medium, a read sensing element, a write element and a capacitive platform, that forms a first electrode and is designed for a voltage potential applied to it independent from a control signal for said read sensing element and for said voltage potential applied to said capacitive platform being independent from a control signal for said write heating element. It further comprises a second electrode arranged in a fixed position relative to the storage medium forming a first capacitor together wherein said first electrode and a medium between the first and second electrode. | 12-25-2008 |
20090003187 | Storage Device and Method for Operating a Storage Device - A method of operating a storage device includes storing data in the form of marks in a storage medium; scanning the storage medium with at least one probe operating in a scanning mode; and utilizing a control unit to provide a pulsed reading signal for data detecting in the scanning mode, and providing the probe with oversampling reading pulses in a clock mark scanning mode, wherein the control unit further comprises an input for a response signal to the oversampling reading pulses, and a determination unit for determining the clock dependent on the response signal; wherein the storage medium comprises marks for determining a clock of the pulsed reading signal. | 01-01-2009 |
20090027242 | HIGH-RATE RLL ENCODING - An unencoded m-bit data input sequence is divided into a block of n bits and a block of m-n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D | 01-29-2009 |
20090089645 | DATA STORAGE SYSTEMS - Method and apparatus for decoding data in a data storage system. In operation, a detector generates an output bit stream in dependence on a data block received from a storage subsystem of the data storage system. A post processor connected to the detector generates a first error corrected bit stream in dependence on the output bit stream and the data block. An error correction decoder connected to the post processor generates a second error corrected bit stream in dependence on the first error corrected bit stream and also generates a checksum in dependence of the second error corrected bit stream. A feedback path supplies from the error correction decoder to the post processor pinning data indicative of locations of correct bits in the second error corrected bit stream in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave. The post processor regenerates the first error corrected bit stream in dependence on the pinning data received from the error correction decoder. | 04-02-2009 |
20090103202 | METHOD FOR AN EQUALIZER COMPUTATION IN A MEDIA SYSTEM USING A DATA SET SEPARATOR SEQUENCE - Provided is a method for receiving a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. A coefficient cyclic equalizer vector is generated as a function of the DSS sequence and the DSS readback sequence. An error signal is generated as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficient cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. | 04-23-2009 |
20090195909 | GAIN CONTROL FOR DATA-DEPENDENT DETECTION IN MAGNETIC STORAGE READ CHANNELS - Method, apparatus and computer program product adjust gain in a read channel of a magnetic media data storage device. A digital signal sample having a data-dependent noise component is received. A gain value, stored in a location in a gain table, is selected in a data-dependent manner. The gain of the signal sample is adjusted in response to the selected gain value. A bit pattern is detected from the gain-adjusted signal sample and a data output signal is output based upon the detected bit pattern. | 08-06-2009 |
20090316773 | WORD SYNCHRONIZATION FOR SERVO READ SIGNALS IN TAPE DRIVES - Methods and apparatus for detecting L-bit sync words occurring at N-bit intervals in PPM-encoded servo pattern read signals read in magnetic tape drives. A soft output detector processes the PPM-encoded servo pattern read signal to produce a series of soft output samples corresponding to respective bits encoded in the servo pattern. A sync word detector then produces block correlation values for respective positions of a sliding L-sample block in the series of soft output samples by (i) calculating at each block position bit correlation values indicating correlation between respective samples and corresponding bits of the sync word and (ii) summing each bit correlation value minus a predetermined function of the corresponding sample value. The sync word detector then detects a sync word at the block position with the maximum block correlation value in an (N+L−1)-sample sequence of the series of soft output samples. | 12-24-2009 |
20100177422 | REWRITE-EFFICIENT ECC/INTERLEAVING FOR MULTI-TRACK RECORDING ON MAGNETIC TAPE - For writing data to multi-track tape, a received data set is received and segmented into unencoded subdata sets, each comprising an array having K | 07-15-2010 |
20100180180 | ECC INTERLEAVING FOR MULTI-TRACK RECORDING ON MAGNETIC TAPE - Conventional C2 coding and interleaving for multi-track data tape in LTO-¾ do not support recording data onto a number of concurrent tracks which is not a power of two. Higher-rate longer C2 codes, which do not degrade error rate performance, are provided. An adjustable format and interleaving scheme accommodates future tape drives in which the number of concurrent tracks is not necessarily a power of two. A data set is segmented into a plurality of unencoded subdata sets and parity bytes are generated for each row and column. The parameters of the C2 code include N | 07-15-2010 |
20110022931 | MEMORY MANAGEMENT IN A NON-VOLATILE SOLID STATE MEMORY DEVICE - A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device, wherein the error is correctable by error-correcting code; and programming the memory unit according to the monitored occurrence of the error; wherein the step of monitoring the occurrence of an error is carried out for at least one block; and wherein said step of programming comprises wear-leveling the monitored block according the error monitored for the monitored block. A computer system and a computer program-product is also provided. | 01-27-2011 |
20110051508 | MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY - A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable to perform in a first programming mode one or more annealing steps to approach the target resistance, wherein the programming scheme is operable to perform in a second programming mode one or more melting steps, wherein the programming scheme is operable to start in the first programming mode and to switch to the second programming mode if the target resistance level of the PCM cell has been undershot in the first programming mode. | 03-03-2011 |
20110069539 | PROGRAMMING MULTI-LEVEL PHASE CHANGE MEMORY CELLS - A method and a feedback controller for programming at least one multi-level phase-change memory cell with a programming signal. The method and feedback controller include a sequence of write pulses applied to the multi-level phase change memory cell, wherein the feedback controller adjusts in real time at least one parameter of each write pulse as a function of a determined resistance error of the phase-change memory cell with respect to a desired reference resistance level. | 03-24-2011 |
20130077394 | MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY - A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable to perform in a first programming mode one or more annealing steps to approach the target resistance, wherein the programming scheme is operable to perform in a second programming mode one or more melting steps, wherein the programming scheme is operable to start in the first programming mode and to switch to the second programming mode if the target resistance level of the PCM cell has been undershot in the first programming mode. | 03-28-2013 |
20130083594 | MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY - A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable to perform in a first programming mode one or more annealing steps to approach the target resistance, wherein the programming scheme is operable to perform in a second programming mode one or more melting steps, wherein the programming scheme is operable to start in the first programming mode and to switch to the second programming mode if the target resistance level of the PCM cell has been undershot in the first programming mode. | 04-04-2013 |
20130117600 | MEMORY MANAGEMENT IN A NON-VOLATILE SOLID STATE MEMORY DEVICE - A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes monitoring an occurrence of an error during a read operation in a memory unit of the device, where the error is correctable by error-correcting code, and programming the memory unit according to the monitored occurrence of the error, where the step of monitoring the occurrence of an error is carried out for at least one block, and wherein said step of programming includes wear-leveling the monitored block according the error monitored for the monitored block. | 05-09-2013 |
20130191704 | MEMORY MANAGEMENT IN A NON-VOLATILE SOLID STATE MEMORY DEVICE - A non-volatile solid state memory device and method for balancing write/erase cycles among blocks to level block usage. The non-volatile solid state memory device includes a memory unit having data stored therein and a controller with logic for programming the memory unit according to a monitored occurrence of an error during a read operation. The method includes monitoring an occurrence of an error during a read operation in a memory unit of the device and programming the memory unit according to the monitored occurrence of the error. | 07-25-2013 |