Patent application number | Description | Published |
20120025845 | SHORT CIRCUIT DETECTION IN AN INKJET PRINTHEAD - A short detection apparatus, system and method detect short circuits in an inkjet printhead using a comparison of measured current consumption and an estimate of current consumption based on print data. The apparatus includes a current sensor to measure current consumed by the printhead to eject a droplet of ink, a current estimator to estimate a current consumption of the printhead due to print data provided to the printhead, and a comparator to compare the measured consumed current to the estimated consumed current. A short circuit in the printhead is indicated when the comparison exceeds a predetermined threshold. | 02-02-2012 |
20120151289 | ELECTRICAL CONNECTIVITY TEST APPARATUS AND METHODS - Methods and apparatus are provided related to testing electrical connectivity. A sequence of distinct test data signal patterns is issued. The test data signals are propagated by way of respective pathways and electrical connectors. A feedback signal is generated in accordance with a test function for each of the test data signal patterns. A test results message is generated in accordance with the feedback signals, which can include specific diagnostic or identifying information. | 06-14-2012 |
20140111818 | Data Flow to a Printing Device - A method of increasing data flow to a printing device includes, with a first raster image processor, converting a document into a first bitmap having a first dot density and representing a black color plane of the document; with a second raster image processor, converting the document into a second bitmap at a second dot density that is a relatively lower dot density than that of the first bitmap, the second bitmap representing other color planes of the document; and transmitting data of the first and second bitmaps to a printing device for printing to a print medium. | 04-24-2014 |
Patent application number | Description | Published |
20080240906 | VARIABLE-VANE ASSEMBLY HAVING FIXED AXIAL-RADIAL GUIDES AND FIXED RADIAL-ONLY GUIDES FOR UNISON RING - A variable-vane assembly for a variable nozzle turbine comprises a nozzle ring supporting a plurality of vanes affixed to vane arms that are engaged in recesses in the inner edge of a unison ring. The unison ring is rotatable about the axis of the nozzle ring so as to pivot the vane arms, thereby pivoting the vanes in unison. A plurality of radial-axial guide pins for the unison ring are inserted into apertures in the nozzle ring and are rigidly affixed therein such that the radial-axial guide pins are non-rotatably secured to the nozzle ring with a guide portion of each radial-axial guide pin projecting axially from the face of the nozzle ring. Each guide portion defines a groove for receiving the inner edge of the unison ring such that the unison ring is restrained by the radial-axial guide pins against excessive movement in both radial and axial directions. | 10-02-2008 |
20100260597 | VARIABLE-VANE ASSEMBLY HAVING FIXED GUIDE PINS FOR UNISON RING - A variable-vane assembly for a variable nozzle turbine comprises a nozzle ring supporting a plurality of vanes affixed to vane arms that are engaged in recesses in the inner edge of a unison ring. The unison ring is rotatable about the axis of the nozzle ring so as to pivot the vane arms, thereby pivoting the vanes in unison. A plurality of guide pins for the unison ring are inserted into apertures in the nozzle ring and are rigidly affixed therein such that the guide pins are non-rotatably secured to the nozzle ring with a guide portion of each guide pin projecting axially from the face of the nozzle ring. Each guide portion defines a shoulder radially overlapping the inner edge of the unison ring such that the unison ring is restrained by the guide pins against excessive movement in both radial and axial directions. | 10-14-2010 |
20130195629 | CONTACTING VANES - An assembly can include vanes and a base configured to seat the vanes at a radial distance about an axis where each vane includes a leading edge and a trailing edge, a pair of lateral surfaces that meet at the leading edge and at the trailing edge, an extension that extends from one of the lateral surfaces and that has a contact surface, and a stop surface to form a contact with a contact surface of another vane to define a minimum flow distance between the vane and the other vane. Various other examples of devices, assemblies, systems, methods, etc., are also disclosed. | 08-01-2013 |
Patent application number | Description | Published |
20090172344 | METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION - A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed. | 07-02-2009 |
20100042779 | Implementing Vector Memory Operations - In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed. | 02-18-2010 |
20100332801 | Adaptively Handling Remote Atomic Execution - In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed. | 12-30-2010 |
20130036268 | Implementing Vector Memory Operations - In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed. | 02-07-2013 |
20130117531 | METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION - A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed. | 05-09-2013 |
20130262771 | INDICATING A LENGTH OF AN INSTRUCTION OF A VARIABLE LENGTH INSTRUCTION SET - Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable length instructions. A plurality of bytes that include an instruction may be read from an instruction cache based on a logical instruction pointer. A determination is made whether a first byte of the plurality of bytes identifies a length of the instruction. In response to detecting that the first byte of the plurality of bytes identifies the length of the instruction, the instruction is read from the plurality of bytes based on the length of the instruction. | 10-03-2013 |
20140052968 | SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTION - A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address. | 02-20-2014 |