Patent application number | Description | Published |
20080218184 | NANOPORE PLATFORMS FOR ION CHANNEL RECORDINGS AND SINGLE MOLECULE DETECTION AND ANALYSIS - Chemical modification of a glass and fused silica nanopore surfaces results in surface properties that are ideal for localized bilayer formation over a nanopore and subsequent ion channel recording. With no surface modification, one may form a bilayer supported on the glass capillary extending across the nanopore orifice. Changing the surface properties from that of bare glass to a moderately hydrophobic surface produces a lipid monolayer above the glass and spontaneously yields a bilayer across the nanopore orifice, effectively corralling a single protein ion channel in the lipid bilayer region spanning nanopore orifice. The bilayer structure over the modified nanopore is such that current can only flow through the protein ion channel. The protein ion channel is able to diffuse in the bilayer above the pore opening, but cannot leave this area to enter the lipid monolayer. The bilayer formed across the nanopore orifice exhibits high electrical breakdown voltage, is stable to mechanical vibrations, and is long lived. Resistance through the protein channel can be measured electrically and is exploited for stochastic single-molecule detection. Protein ion channels can be inserted and removed from the bilayer by adjusting transmembrane pressure, and adapter molecules can be electrostatically trapped in the ion channel by applying high transmembrane voltages. | 09-11-2008 |
20090142504 | Method and Apparatus for Single Side Bilayer Formation - An apparatus for single-sided bilayer formation includes a first fluid chamber including a sidewall and a second fluid chamber extending through the sidewall. A barrier wall separates the first and second fluid chambers and includes a nanopore therein across which a planar lipid bilayer (PLB) is formed. In use, an electrolyte is added to the first and second fluid chambers and a lipid/organic solvent mixture is added to the first fluid chamber to form a lipid/organic solvent layer. The electrolyte level within the first fluid chamber is adjusted such that the lipid layer is raised above the barrier wall and a PLB is formed. Electrolyte levels may be adjusted manually or utilizing a fluid level regulator with or without feedback control. Optionally, the apparatus may be in the form of a nanopore array. The apparatus may be incorporated into an ion channel sensing system wherein an electrical current through each PLB is separately recorded. | 06-04-2009 |
20100025263 | NANOPORE PARTICLE ANALYZER, METHOD OF PREPARATION AND USE THEREOF - Provided are the preparation, characterization, and application of a nanopore membrane device. The nanopore device comprises a thin membrane prepared from glass, fused silica, ceramics or quartz, containing one or more nanopores ranging from about 2 nm to about 500 nm. The nanopore is prepared by a template method using sharpened metal wires and the size of the pore opening can be controlled during fabrication by an electrical feedback circuit. The nanopore device is particularly useful for counting and analyzing nanoparticles of radius less than 400 nm. | 02-04-2010 |
20100320094 | Nanopore Platforms for Ion Channel Recordings and Single Molecule Detection and Analysis - A nanopore device includes a membrane having a nanopore extending there through forming a channel from a first side of the membrane to a second side of the membrane. The surface of the channel and first side of the membrane are modified with a hydrophobic coating. A first lipid monolayer is deposited on the first side of the membrane, and a second lipid monolayer is deposited on the second side of the membrane, wherein the hydrophobic coating causes spontaneous generation of a lipid bilayer across the nanopore orifice. Sensing entities, such as a protein ion channel, can be inserted and removed from the bilayer by adjusting transmembrane pressure, and adapter molecules can be electrostatically trapped in the ion channel by applying high transmembrane voltages, while resistance or current flow through the sensing entity can be measured electrically. | 12-23-2010 |
20110168551 | Nanopore Electrode, Nanopore Membrane, Methods of Preparation and Surface Modification, and Use Thereof - Provided are fabrication, characterization and application of a nanodisk electrode, a nanopore electrode and a nanopore membrane. These three nanostructures share common fabrication steps. In one embodiment, the fabrication of a disk electrode involves sealing a sharpened internal signal transduction element (“ISTE”) into a substrate, followed by polishing of the substrate until a nanometer-sized disk of the ISTE is exposed. The fabrication of a nanopore electrode is accomplished by etching the nanodisk electrode to create a pore in the substrate, with the remaining ISTE comprising the pore base. Complete removal of the ISTE yields a nanopore membrane, in which a conical shaped pore is embedded in a thin membrane of the substrate. | 07-14-2011 |
20140216933 | HIGH CONTRAST SIGNAL TO NOISE RATIO DEVICE COMPONENTS - Provided are device components, devices and methods characterized by a high contrast signal to noise ratio (CNR). | 08-07-2014 |
20140248608 | METHODS FOR CHARACTERIZING A DEVICE COMPONENT BASED ON A CONTRAST SIGNAL TO NOISE RATIO - The general concept of using a nanopore for DNA sequencing is to electrophoretically drive a polymer (e.g. single stranded DNA) through a nanopore under aqueous conditions, and identify each individual monomer (e.g. nucleotide) of the strand as it passes through the sensitive region of the nanopore based on its characteristic current modulation. | 09-04-2014 |
20150329600 | MODIFIED ALPHA HEMOLYSIN POLYPEPTIDES AND METHODS OF USE - Provided herein are alpha hemolysin polypeptides comprising modified amino acid sequences that can reduce the rate of translocation of a polymer. Also provided herein are apparatuses and devices comprising modified hemolysin polypeptides. Also provided herein are methods of using modified alpha hemolysin proteins for use in characterizing and/or sequencing a polymer or for use as molecular sensors. | 11-19-2015 |
Patent application number | Description | Published |
20100278984 | Health characteristic non-standardized or standardized high cocoa dark chocolate with improved taste texture, melt, creaminess and reduced bitterness - The present invention provides for a non-standardized dark chocolate composition to have up to | 11-04-2010 |
20110287134 | CHOCOLATE DIETARY FIBER SUPPLEMENT AND DELIVERY METHOD - Chocolate or compound coating based fiber compositions, which have at least about 20% of a fiber component, by weight of the formula, that provide a safe and effective amount of fiber component to a user are disclosed. This delivery method can utilize either a bulk forming fiber like psyllium, or a non-bulk forming fiber like inulin or a combination of both types of fiber components. The fiber easily can be incorporated into the compositions without adversely affecting the stability, feel, and taste of the compositions. The nutritional profiles of these fiber compositions are consistent with dietary guidelines, which physicians follow when prescribing fiber compositions as supplements or for cholesterol reduction purposes. Also disclosed is a method of producing such compositions and a method of providing a safe and effective amount of fiber component to a user. | 11-24-2011 |
20110288182 | HEALTH CHARACTERISTIC DULCE DE LECHE CONFECTION COMPOSITIONS AND FLAVORED MILK - The present invention provides for Dulce de Leche confection compositions and Dulce de Leche based flavored milk that has an improved, healthier fat structure, unique antioxidant taste profile, lower sugar content, fiber component, and a 0% or greater supplement component that can add additional dietary benefits. Cholesterol reduction can be accomplished within certain embodiments of this invention. Specific ratios of ingredients within our compositions create a taste, texture, mouth feel, and rich and creamy true Dulce de Leche confection without the negative health ramifications of high milk fat content and sugar content characteristic of traditional Dulce de Leche products. Additionally, the method for preparing these Dulce de Leche confection products and flavored milk are covered. | 11-24-2011 |
20110313055 | HEALTH CHARACTERISTIC CHEWY OR GUMMY CANDY CONFECTION - The present invention provides for flavored chewy or gummy candy confections made by making a flavored chewy or gummy candy confection from scratch or adjusting a current flavored chewy or gummy candy confection brand product with our invention. This invention can have a healthier group of edible oils component, unique antioxidant taste profile component, fiber component, water component, emulsifier component, and potentially a 0% or greater supplement component that can add additional dietary benefits. Specific ratios of ingredients can lower sugar content up to 75% while creating a product with a taste, texture, and mouth feel similar to regular flavored chewy or gummy candy. The reduction of sugar possible within this invention can reduce the negative health ramifications of high sugar content that current flavored chewy or gummy candy confections suffer from and the addition of the healthier ingredients adds some improved health characteristics to the products that usually are devoid of nutrition. Additionally, the method for preparing a flavored chewy or gummy candy confection with these improved health characteristics, taste profile, and dietary benefits are covered. | 12-22-2011 |
20120171331 | GROUND BEEF OR PROCESSED MEATS WITH IMPROVED HEALTH AND RHEOLOGICAL CHARACTERISTICS - The present embodiments include a ground meat, processed meat, game meat, or sausage that has improved health and taste characteristics. The embodiments include the addition to the meat of a fat emulsion that includes a healthier group of edible oils component, fiber component, water component, and other components that can add additional dietary benefits. | 07-05-2012 |
20140080906 | FAT EMULSION PROVIDING TASTE MASKING FOR ACTIVE HEALTH AND WELLNESS INGREDIENTS - The embodiments relate to fat emulsion structures based on both an aqueous and non-aqueous glycerin component as the primary aqueous component in which the fat emulsion can create a wide range of viscosities that mimic fat structures similar to cream, or all the way to hardened fat structures like Trans Fat. The fat emulsion can be added to a wide group of foods that use a monosaccharide or disaccharide as the basis for its sweetener component, can lower the sugar content of foods, can improve mouth feel while lowering the fat content in high fat foods, can add a balance of dietary fats and fiber to foods, and can add antioxidant content to food products. The fat emulsion also can be used as a taste masking composition to mask the taste of unpalatable active ingredients or unpalatable components that may be added to the emulsion. | 03-20-2014 |
Patent application number | Description | Published |
20100278977 | Health characteristic Caramel Flavored Confection, Chews, Hard Candy, and Caramel Flavored Milk - The present invention provides for caramel flavored confections, chews, hard candies or caramel flavored milk that has an improved, healthier fat structure, unique antioxidant taste profile, fiber component, and a 0% or greater supplement component that can add additional dietary benefits. Cholesterol reduction and cardiovascular health and removal of cholesterol from the bloodstream can be accomplished within certain compositions of this invention. Specific ratios of ingredients create a taste, texture, to mouthfeel, and rich flavor similar to a high milk fat or butter fat based caramel without the negative health ramifications of high milk fat based type caramels. Additionally, the method for preparing a caramel flavored confection, chews, and milk with these improved health characteristics, taste profile, and dietary benefits are covered. | 11-04-2010 |
20100278978 | Reduced Milk Fat Non-standardized Milk Chocolate (Milk Fat Free/Low Milk fat) and Standardized Reduced Milk Fat Milk Chocolate with Improved Health Characteristics - A reduced milk fat, reduced sugar, improved health characteristic, higher antioxidant content, improved taste, texture, melt, and creaminess non-standardized milk chocolate that can have a milk fat content of 0% to 8% and is blended with a standardized chocolate, an edible oil blend, 100% Cocoa Powder, Confectionery Sugar, Cocoa Seed Butter Crystals, and synergistic antioxidant flavor blend including; Virgin Coconut Oil, Vanilla Powder, Blackberry, and Acai Berry. A standardized milk chocolate product with 3.69% or higher milk fat that has improved health characteristics , higher antioxidant content, improved taste, texture, melt, and creaminess from a synergistic antioxidant flavor blend including; Virgin Coconut Oil, Vanilla Powder, Blackberry, and Acai Berry. The ingredients are in specific amounts and ratios such that they can be easily incorporated into the compositions without adversely affecting the stability or feel, and actually improve taste, texture, melt, and creaminess as well as improve health characteristics of the compositions. The compositions can be manufactured and sold in any format that current chocolate confectionery products are sold in including; squares, tablet bars, molded shapes, as coatings or as enrobing material, or as ingredients in foods that have chocolate or chocolate compositions in them, etc. Additionally the process for preparing such compositions is provided. | 11-04-2010 |
20100278981 | Meal Replacement and Appetite Control/ Diet System - The present invention provides a composition of nutritive based ingredients that together provide a source of balanced and provides the ability to control food cravings, increase satiety, promote a feeling of fullness and provide a user a method to maintain a healthy weight and or achieve weight loss. This composition of ingredients includes a chocolate or caramel flavored confection component, a high protein component, a fiber blend component, an edible oil component, an antioxidant component from natural occurring sources, a supplement component that can provide specific health benefits as well as a balanced group of vitamins and minerals. The composition of ingredients can be delivered in a variety of food platforms. A functional food confectionery is a preferred platform for our invention delivery system. Portion control bars and/or bars that have pre-determined break points that control portion size and portioned squares or other shapes would be the preferred product structure. A complete weight loss and weight maintenance methodology, including use instructions for incorporating the products within the daily diet is identified. Methods of manufacturing and compositions are also included. | 11-04-2010 |
20110287134 | CHOCOLATE DIETARY FIBER SUPPLEMENT AND DELIVERY METHOD - Chocolate or compound coating based fiber compositions, which have at least about 20% of a fiber component, by weight of the formula, that provide a safe and effective amount of fiber component to a user are disclosed. This delivery method can utilize either a bulk forming fiber like psyllium, or a non-bulk forming fiber like inulin or a combination of both types of fiber components. The fiber easily can be incorporated into the compositions without adversely affecting the stability, feel, and taste of the compositions. The nutritional profiles of these fiber compositions are consistent with dietary guidelines, which physicians follow when prescribing fiber compositions as supplements or for cholesterol reduction purposes. Also disclosed is a method of producing such compositions and a method of providing a safe and effective amount of fiber component to a user. | 11-24-2011 |
20110288182 | HEALTH CHARACTERISTIC DULCE DE LECHE CONFECTION COMPOSITIONS AND FLAVORED MILK - The present invention provides for Dulce de Leche confection compositions and Dulce de Leche based flavored milk that has an improved, healthier fat structure, unique antioxidant taste profile, lower sugar content, fiber component, and a 0% or greater supplement component that can add additional dietary benefits. Cholesterol reduction can be accomplished within certain embodiments of this invention. Specific ratios of ingredients within our compositions create a taste, texture, mouth feel, and rich and creamy true Dulce de Leche confection without the negative health ramifications of high milk fat content and sugar content characteristic of traditional Dulce de Leche products. Additionally, the method for preparing these Dulce de Leche confection products and flavored milk are covered. | 11-24-2011 |
20110313055 | HEALTH CHARACTERISTIC CHEWY OR GUMMY CANDY CONFECTION - The present invention provides for flavored chewy or gummy candy confections made by making a flavored chewy or gummy candy confection from scratch or adjusting a current flavored chewy or gummy candy confection brand product with our invention. This invention can have a healthier group of edible oils component, unique antioxidant taste profile component, fiber component, water component, emulsifier component, and potentially a 0% or greater supplement component that can add additional dietary benefits. Specific ratios of ingredients can lower sugar content up to 75% while creating a product with a taste, texture, and mouth feel similar to regular flavored chewy or gummy candy. The reduction of sugar possible within this invention can reduce the negative health ramifications of high sugar content that current flavored chewy or gummy candy confections suffer from and the addition of the healthier ingredients adds some improved health characteristics to the products that usually are devoid of nutrition. Additionally, the method for preparing a flavored chewy or gummy candy confection with these improved health characteristics, taste profile, and dietary benefits are covered. | 12-22-2011 |
20120171331 | GROUND BEEF OR PROCESSED MEATS WITH IMPROVED HEALTH AND RHEOLOGICAL CHARACTERISTICS - The present embodiments include a ground meat, processed meat, game meat, or sausage that has improved health and taste characteristics. The embodiments include the addition to the meat of a fat emulsion that includes a healthier group of edible oils component, fiber component, water component, and other components that can add additional dietary benefits. | 07-05-2012 |
20140080906 | FAT EMULSION PROVIDING TASTE MASKING FOR ACTIVE HEALTH AND WELLNESS INGREDIENTS - The embodiments relate to fat emulsion structures based on both an aqueous and non-aqueous glycerin component as the primary aqueous component in which the fat emulsion can create a wide range of viscosities that mimic fat structures similar to cream, or all the way to hardened fat structures like Trans Fat. The fat emulsion can be added to a wide group of foods that use a monosaccharide or disaccharide as the basis for its sweetener component, can lower the sugar content of foods, can improve mouth feel while lowering the fat content in high fat foods, can add a balance of dietary fats and fiber to foods, and can add antioxidant content to food products. The fat emulsion also can be used as a taste masking composition to mask the taste of unpalatable active ingredients or unpalatable components that may be added to the emulsion. | 03-20-2014 |
Patent application number | Description | Published |
20110201161 | METHOD OF FORMING A BURIED PLATE BY ION IMPLANTATION - A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor substrate. Straggle of the implanted ions form a doped region that laterally extends beyond a horizontal cross-sectional area of the opening. A deep trench is formed by performing an anisotropic etch of a semiconductor material underneath the opening to a depth above a deep end of an implanted region. Ion implantation steps and anisotropic etch steps are alternately employed to extend the depth of the doped region and the depth of the deep trench, thereby forming a doped region around a deep trench that has narrow lateral dimensions. The doped region can be employed as a buried plate for a deep trench capacitor. | 08-18-2011 |
20110215412 | STRUCTURE AND METHOD TO FABRICATE pFETS WITH SUPERIOR GIDL BY LOCALIZING WORKFUNCTION - A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing. | 09-08-2011 |
20110272762 | EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR - A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region. | 11-10-2011 |
20110291169 | REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD - A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor. | 12-01-2011 |
20120068237 | SELF-ALIGNED STRAP FOR EMBEDDED CAPACITOR AND REPLACEMENT GATE DEVICES - After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor. | 03-22-2012 |
20120122315 | SELF-ALIGNED DEVICES AND METHODS OF MANUFACTURE - A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate. | 05-17-2012 |
20120305998 | HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY - In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array. | 12-06-2012 |
20130183806 | High Density Memory Cells Using Lateral Epitaxy - In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array. | 07-18-2013 |
20130189826 | Reduced Corner Leakage in SOI Structure and Method - A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor. | 07-25-2013 |
20130214382 | METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE - A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided. | 08-22-2013 |
20130230949 | EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR - A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region. | 09-05-2013 |
20130267071 | SELF-ALIGNED STRAP FOR EMBEDDED CAPACITOR AND REPLACEMENT GATE DEVICES - After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor. | 10-10-2013 |
20140154849 | METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE - A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided. | 06-05-2014 |
Patent application number | Description | Published |
20110316061 | STRUCTURE AND METHOD TO CONTROL BOTTOM CORNER THRESHOLD IN AN SOI DEVICE - Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure. | 12-29-2011 |
20120064694 | FORMING IMPLANTED PLATES FOR HIGH ASPECT RATIO TRENCHES USING STAGED SACRIFICIAL LAYER REMOVAL - A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other. | 03-15-2012 |
20120104547 | LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure. | 05-03-2012 |
20120139085 | Structure and Method for Topography Free SOI Integration - A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer. | 06-07-2012 |
20120261797 | LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI. | 10-18-2012 |
20120306049 | METAL TRENCH CAPACITOR AND IMPROVED ISOLATION AND METHODS OF MANUFACTURE - A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material. | 12-06-2012 |
20120326233 | METHOD TO REDUCE THRESHOLD VOLTAGE VARIABILITY WITH THROUGH GATE WELL IMPLANT - The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer. | 12-27-2012 |
20130105898 | Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices | 05-02-2013 |
20130134527 | STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT - A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit. | 05-30-2013 |
20130146957 | EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE FORMED IN AN EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATE - A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill. | 06-13-2013 |
20130147007 | DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions. | 06-13-2013 |
20130154007 | RARE-EARTH OXIDE ISOLATED SEMICONDUCTOR FIN - A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion. | 06-20-2013 |
20130181326 | MULTILAYER MIM CAPACITOR - An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers. | 07-18-2013 |
20130193562 | STRUCTURE AND METHOD FOR TOPOGRAPHY FREE SOI INTEGRATION - A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer. | 08-01-2013 |
20130207188 | JUNCTION BUTTING ON SOI BY RAISED EPITAXIAL STRUCTURE AND METHOD - A method of forming a semiconductor device including forming well trenches on opposing sides of a gate structure by removing portions of a semiconductor on insulator (SOI) layer of an semiconductor on insulator (SOI) substrate, wherein the base of the well trenches is provided by a surface of a buried dielectric layer of the SOI substrate and sidewalls of the well trenches are provided by a remaining portion of the SOI layer. Forming a dielectric fill material at the base of the well trenches, wherein the dielectric fill material is in contact with the sidewalls of the well trenches and at least a portion of the surface of the buried dielectric layer that provides the base of the well trenches. Forming a source region and a drain region in the well trenches with an in-situ doped epitaxial semiconductor material. | 08-15-2013 |
20130328157 | SPACER ISOLATION IN DEEP TRENCH - A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening. | 12-12-2013 |
20130328161 | SPACER ISOLATION IN DEEP TRENCH - A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening. | 12-12-2013 |
20140061793 | SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY - A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device. | 03-06-2014 |
20140070292 | DEEP TRENCH CAPACITOR - A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer. | 03-13-2014 |
20140073092 | RECESSED SINGLE CRYSTALLINE SOURCE AND DRAIN FOR SEMICONDUCTOR-ON-INSULATOR DEVICES - After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer. | 03-13-2014 |
20140084418 | LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer including a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer including a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI. | 03-27-2014 |
20140120688 | DEEP ISOLATION TRENCH STRUCTURE AND DEEP TRENCH CAPACITOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions. | 05-01-2014 |
20140170854 | SELF-ALIGNED DEVICES AND METHODS OF MANUFACTURE - A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the patterned line to the substrate. | 06-19-2014 |
20150014814 | METAL TRENCH CAPACITOR AND IMPROVED ISOLATION AND METHODS OF MANUFACTURE - A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material. | 01-15-2015 |
20150037939 | RARE-EARTH OXIDE ISOLATED SEMICONDUCTOR FIN - A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion. | 02-05-2015 |
20150054130 | MULTILAYER MIM CAPACITOR - An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers. | 02-26-2015 |
20150221715 | DEEP TRENCH CAPACITOR - A deep trench capacitor structure including an SOI substrate comprising an SOI layer, a rare earth oxide layer, and a bulk substrate, the rare earth oxide layer is located below the SOI layer and above the bulk substrate, and the rare earth oxide layer insulates the SOI layer from the bulk substrate, and a deep trench capacitor extending from a top surface of the SOI layer, through the rare earth oxide layer, down to a location within the bulk substrate, the rare earth oxide layer contacts the deep trench capacitor at an interface between the rare earth oxide layer and the bulk substrate forming an incline away from the deep trench capacitor. | 08-06-2015 |
20150287721 | SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY - A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device. | 10-08-2015 |
Patent application number | Description | Published |
20100091960 | INTERACTIVE VOICE RESPONSE SYSTEM AND METHOD WITH COMMON INTERFACE AND INTELLIGENT AGENT MONITORING - A modular interactive voice recognition (“IVR”) overlay system and a method of processing calls. The system provides an application server, a plurality of agent workstations and a graphical user interface (“GUI”) to allow a hybrid approach to processing calls using an automated IVR and live agents. The system and method allow a single agent to process multiple calls simultaneously and is compatible with existing IVR systems and can be implemented as an add-on to existing IVR systems. | 04-15-2010 |
20110133948 | METHOD, SYSTEM AND APPARATUS FOR CONTROLLING PATIENT ACCESS TO MEDICAMENTS - A method, system and apparatus for controlling and tracking patient access to medicaments. A patient is provided with medication in locked pill containers that must be unlocked with an access code before the patient can access a limited quantity of medication in each container. Thus the patient is forced to go through an interactive session periodically with a master system, via a communicative intermediary, in order to obtain a valid passcode for each batch of medications and follow a treatment regimen. The patient may be assessed during each interaction with the master system. That assessment can include various questions, including questions about status codes that may optionally be displayed on each medication container. These status codes may optionally encode detail about the patient's pattern of accessing medication. The general rate of medication usage can also be deduced by the rate at which the patient contacts the master system. After patient assessment, the master system may elect to not provide the patient with an access code, typically if the patient meets certain criteria that indicate overuse of the medication. Conversely, the master system can elect to proactively contact the patient if the patient fails to make contact with the master system at an expected time, as this lack of contact suggests that the patient is underusing the medication and requires a reminder. | 06-09-2011 |
20130226339 | METHOD, SYSTEM AND APPARATUS FOR CONTROLLING PATIENT ACCESS TO MEDICAMENTS - Systems and methods for detecting a likely misuse of a medicament by a user. The system includes a computer communicatively coupled with a dispensing device. The computer receives a usage pattern of a medicament by the user as indicated by the dispensing device and a result of a test correlating with an actual consumption of the medicament by the user. Based on the usage pattern, the computer computes an estimated result of a test corresponding to the at least one predetermined test. Based on a comparison between the estimated result and the test result, a determination is made as to whether the user has likely misused the medicament. | 08-29-2013 |
20140079208 | INTERACTIVE VOICE RESPONSE SYSTEM AND METHOD WITH COMMON INTERFACE AND INTELLIGENT AGENT MONITORING - A modular interactive voice recognition (“IVR”) overlay system and a method of processing calls. The system provides an application server, a plurality of agent workstations and a graphical user interface (“GUI”) to allow a hybrid approach to processing calls using an automated IVR and live agents. The system and method allow a single agent to process multiple calls simultaneously and is compatible with existing IVR systems and can be implemented as an add-on to existing IVR systems. | 03-20-2014 |
20140195043 | METHOD, SYSTEM AND APPARATUS FOR CONTROLLING PATIENT ACCESS TO MEDICAMENTS - A method, system and apparatus for controlling and tracking patient access to medicaments. A patient is provided with medication in locked pill containers that must be unlocked with an access code before the patient can access a limited quantity of medication in each container. Thus the patient is forced to go through an interactive session periodically with a master system, via a communicative intermediary, in order to obtain a valid passcode for each batch of medications and follow a treatment regimen. The patient may be assessed during each interaction with the master system. That assessment can include various questions, including questions about status codes that may optionally be displayed on each medication container. These status codes may optionally encode detail about the patient's pattern of accessing medication. The general rate of medication usage can also be deduced by the rate at which the patient contacts the master system. After patient assessment, the master system may elect to not provide the patient with an access code, typically if the patient meets certain criteria that indicate overuse of the medication. Conversely, the master system can elect to proactively contact the patient if the patient fails to make contact with the master system at an expected time, as this lack of contact suggests that the patient is underusing the medication and requires a reminder. | 07-10-2014 |
20140294162 | INTERACTIVE VOICE RESPONSE SYSTEM AND METHOD WITH COMMON INTERFACE AND INTELLIGENT AGENT MONITORING - A modular interactive voice recognition (“IVR”) overlay system and a method of processing calls. The system provides an application server, a plurality of agent workstations and a gaphical user interface (“GUI”) to allow a hybrid approach to processing calls using an automated IVR and live agents. The system and method allow a single agent to process multiple calls simultaneously and is compatible with existing IVR systems and can be implemented as an add-on to existing IVR systems. | 10-02-2014 |
20160117480 | METHOD, SYSTEM AND APPARATUS FOR CONTROLLING PATIENT ACCESS TO MEDICAMENTS - Systems and methods for detecting a likely misuse of a medicament by a user. The system includes a computer communicatively coupled with a dispensing device. The computer receives a usage pattern of a medicament by the user as indicated by the dispensing device and a result of a test correlating with an actual consumption of the medicament by the user. Based on the usage pattern, the computer computes an estimated result of a test corresponding to the at least one predetermined test. Based on a comparison between the estimated result and the test result, a determination is made as to whether the user has likely misused the medicament. | 04-28-2016 |