Patent application number | Description | Published |
20110320643 | MEASUREMENT FACILITY FOR ADAPTER FUNCTIONS - A measurement facility is provided for capturing and presenting fine-grained usage information for adapter functions in an input/output subsystem. Adapter specific input/output traffic is tracked on a per function basis and the results are dynamically presented to the user. This information is useful for performance tuning, load balancing and usage based charging, as examples. | 12-29-2011 |
20110320653 | SYSTEM AND METHOD FOR ROUTING I/O EXPANSION REQUESTS AND RESPONSES IN A PCIE ARCHITECTURE - A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters at I/O adapter addresses, the I/O hub including logic for implementing a method comprising receiving requests from the plurality of I/O adapters, storing the I/O adapter addresses of a requester along with their corresponding target recipient addresses and operation codes, receiving a response from a responder, the response indicating that a request has been completed, determining that the response is in a format other than a format supported by the I/O bus, transforming the response into the format supported by the I/O bus, locating a stored I/O adapter address having a corresponding target recipient address that matches the responder address and a corresponding operation code that matches the responder operation code, and transmitting the response to the stored I/O adapter address. | 12-29-2011 |
20110320666 | INPUT/OUTPUT (I/O) EXPANSION RESPONSE PROCESSING IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) ENVIRONMENT - A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester. | 12-29-2011 |
20110320674 | UPBOUND INPUT/OUTPUT EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIE ARCHITECTURE - A system for implementing non-standard I/O adapters in a standardized input/output (I/O) architecture, the system comprising an I/O adapter communicatively coupled to an I/O hub via an I/O bus, the I/O adapter communicating in a first protocol, the I/O bus communicating in a second protocol different than the first protocol, and the I/O adapter including logic for implementing a method comprising initiating a first request to perform an operation on a host system, the first request formatted for the first protocol and comprising data required to process the first request, and creating a second request responsive to the first request, the second request comprising a header and formatted according to the second protocol, the creating comprising storing the data required to process the first request in the header of the second request. The method further comprising sending the second request to the host system. | 12-29-2011 |
20110320675 | SYSTEM AND METHOD FOR DOWNBOUND I/O EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIe ARCHITECTURE - A system for implementing non-standard I/O adapters in a standardized I/O architecture, the system comprising an I/O hub communicatively coupled to an I/O bus and at least one I/O adapter, the I/O hub including logic for implementing a method, the method comprising receiving a request to perform an operation on the I/O adapter from a requester at a requester address, the I/O adapter at a destination address, determining that the request is in a format other than a format supported by the I/O bus, the I/O bus expecting a requester identifier at a first location in a header of the request, reformatting the request into the format supported by the I/O bus, the reformatting comprising storing the requester address, the destination address and an operation code at the first location in the header of the reformatted request, and sending the reformatted request to the I/O adapter. | 12-29-2011 |
20110320703 | ASSOCIATING INPUT/OUTPUT DEVICE REQUESTS WITH MEMORY ASSOCIATED WITH A LOGICAL PARTITION - An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory. | 12-29-2011 |
20110320756 | RUNTIME DETERMINATION OF TRANSLATION FORMATS FOR ADAPTER FUNCTIONS - Various address translation formats are available for use in obtaining system memory addresses for use by requestors, such as adapter functions, in accessing system memory. The particular address translation format to be used by a given requestor is pre-registered in a device table entry associated with that requestor. | 12-29-2011 |
20110320758 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 12-29-2011 |
20110320887 | SCALABLE I/O ADAPTER FUNCTION LEVEL ERROR DETECTION, ISOLATION, AND REPORTING - A system for implementing scalable input/output (I/O) function level error detection, isolation, and reporting, the system comprising, an I/O hub communicatively coupled to a computer processor, system memory and at least one I/O adapter, the at least one I/O adapter include a function and the I/O hub including logic for implementing a method. The method comprising detecting an error in a communication initiated between the function and the system memory, the communication including an I/O request from an application. The method further comprising preventing future communication between the one function and the system memory in response to the detecting. The method additionally comprising notifying the application that the error in communication occurred in response to the detecting. | 12-29-2011 |
20110321061 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions. | 12-29-2011 |
20120036298 | INTERRUPT SOURCE CONTROLLER WITH SCALABLE STATE STRUCTURES - A data processing system includes a processor core, a system memory, coupled to the processor core, that includes an interrupt data structure including a plurality of entries each associated with a respective one of a plurality of interrupts. An input/output (I/O) subsystem including at least one I/O host bridge and a plurality of partitionable endpoints (PEs) each having an associated PE number. The I/O host bridge, responsive to receiving a message signaled interrupt (MSI) including at least a message address, determines from the message address a system memory address of a particular entry among the plurality of entries in the interrupt data structure, accesses the particular entry, and, based upon contents of the particular entry, validates authorization of an interrupt source to issue the MSI and presents an interrupt associated with the particular entry for service. | 02-09-2012 |
20120036302 | DETERMINATION OF ONE OR MORE PARTITIONABLE ENDPOINTS AFFECTED BY AN I/O MESSAGE - A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message. | 02-09-2012 |
20120036304 | INJECTION OF I/O MESSAGES - A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer. | 02-09-2012 |
20120036305 | DETERMINATION VIA AN INDEXED STRUCTURE OF ONE OR MORE PARTITIONABLE ENDPOINTS AFFECTED BY AN I/O MESSAGE - A data processing system includes a processor core, a system memory including a first data structure including entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers and a second data structure, and an input/output (I/O) subsystem including an I/O bridge and a plurality of PEs each including one or more requesters each having a respective requester ID. The I/O host bridge, responsive to receiving an I/O message including a requester ID, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index, where the second entry indicating one or more of the plurality of PEs affected by the message. The I/O host bridge services the I/O message with reference to each of the plurality of PEs indicated by the second entry. | 02-09-2012 |
20120185632 | IMPLEMENTING PCI-EXPRESS MEMORY DOMAINS FOR SINGLE ROOT VIRTUALIZED DEVICES - A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB. | 07-19-2012 |
20120203934 | DETERMINATION OF ONE OR MORE PARTITIONABLE ENDPOINTS AFFECTED BY AN I/O MESSAGE - A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message. | 08-09-2012 |
20120203939 | INJECTION OF I/O MESSAGES - A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer. | 08-09-2012 |
20120221757 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions. | 08-30-2012 |
20130067194 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 03-14-2013 |
20130073759 | UPBOUND INPUT/OUTPUT EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIE ARCHITECTURE - Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system. | 03-21-2013 |
20130073766 | INPUT/OUTPUT (I/O) EXPANSION RESPONSE PROCESSING IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) ENVIRONMENT - Embodiments of the invention relate to non-standard input/output (I/O) adapters in a standardized I/O architecture. An aspect of the invention includes implementing non-standard I/O adapters in a standardized I/O architecture. A request is received at an I/O adapter from a requester to perform an operation on one of the I/O adapters. It is determined that the request is in a format other than a format supported by an I/O bus and that the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus, and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus. The completion response is transmitted to the requester. | 03-21-2013 |
20130073767 | INPUT/OUTPUT (I/O) EXPANSION RESPONSE PROCESSING IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) ENVIRONMENT - A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester. | 03-21-2013 |
20130086435 | SCALABLE I/O ADAPTER FUNCTION LEVEL ERROR DETECTION, ISOLATION, AND REPORTING - Embodiments of the invention relate to scalable input/output (I/O) function level error detection, isolation, and reporting. An aspect of the invention includes detecting an error in a communication initiated between the function and a system memory, the communication including an I/O request from an application. Future communication is prevented between the one function and the system memory in response to the detecting. The application is notified that the error in communication occurred in response to the detecting. | 04-04-2013 |
20140129795 | CONFIGURABLE I/O ADDRESS TRANSLATION DATA STRUCTURE - In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased. | 05-08-2014 |
20140129796 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 05-08-2014 |
20140129797 | CONFIGURABLE I/O ADDRESS TRANSLATION DATA STRUCTURE - In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased. | 05-08-2014 |
20150067224 | DIRECT MEMORY ACCESS (DMA) ADDRESS TRANSLATION WITH A CONSECUTIVE COUNT FIELD - DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries. | 03-05-2015 |
20150067297 | DIRECT MEMORY ACCESS (DMA) ADDRESS TRANSLATION WITH A CONSECUTIVE COUNT FIELD - DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries. | 03-05-2015 |