Patent application number | Description | Published |
20090001341 | Phase Change Memory with Tapered Heater - An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. | 01-01-2009 |
20090046493 | METHOD AND APPARATUS FOR FABRICATING SUB-LITHOGRAPHY DATA TRACKS FOR USE IN MAGNETIC SHIFT REGISTER MEMORY DEVICES - In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section. | 02-19-2009 |
20090111228 | SELF ALIGNED RING ELECTRODES - The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed. | 04-30-2009 |
20090186443 | METHOD TO ENHANCE PERFORMANCE OF COMPLEX METAL OXIDE PROGRAMMABLE MEMORY - A method of incorporating oxygen vacancies near an electrode/oxide interface region of a complex metal oxide programmable memory cell which includes forming a first electrode of a metallic material which remains metallic upon oxidation, forming a second electrode facing the first electrode, forming an oxide layer in between the first and second electrodes, applying an electrical signal to the first electrode such that oxygen ions from the oxide layer are embedded in and oxidize the first electrode, and forming oxygen vacancies near the electrode/oxide interface region of the complex metal oxide programmable memory cell. | 07-23-2009 |
20090189139 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 07-30-2009 |
20090275168 | PHASE CHANGE MATERIAL WITH FILAMENT ELECTRODE - The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode. | 11-05-2009 |
20090289242 | Phase Change Memory With Tapered Heater - An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. | 11-26-2009 |
20100048020 | Nanoscale Electrodes for Phase Change Memory Devices - A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions. | 02-25-2010 |
20100078617 | METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer. | 04-01-2010 |
20100078621 | METHOD TO REDUCE RESET CURRENT OF PCM USING STRESS LINER LAYERS - A memory cell structure and method for forming the same. The method includes forming a via within a dielectric layer. The via is formed over the center of an electrically conducting bottom electrode. The method includes depositing a stress liner along at least one sidewall of the via. The stress liner imparting stress on material proximate the stress liner. In one embodiment, the stress liner provides a stress in the range of 500 to 5000 MPa on the material enclosed within its volume. The method includes depositing phase change material within the via and the volume enclosed by the stress liner. The method also includes forming an electrically conducting top electrode above the phase change material. | 04-01-2010 |
20110001111 | THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 01-06-2011 |
20110037042 | PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL - A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell. | 02-17-2011 |
20110049655 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 03-03-2011 |
20110057162 | IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER - A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material. | 03-10-2011 |
20110186800 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 08-04-2011 |
20110240944 | PHASE CHANGE MEMORY DEVICE WITH PLATED PHASE CHANGE MATERIAL - A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell. | 10-06-2011 |
20120008362 | Magnetic Spin Shift Register Memory - A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material. | 01-12-2012 |
20120037877 | ONE-MASK PHASE CHANGE MEMORY PROCESS INTEGRATION - An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal | 02-16-2012 |
20120038056 | INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN - The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask. | 02-16-2012 |
20120108024 | FIELD EFFECT TRANSISTOR HAVING NANOSTRUCTURE CHANNEL - A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure. | 05-03-2012 |
20120112154 | IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER - A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material. | 05-10-2012 |
20120115302 | METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer. | 05-10-2012 |
20120126194 | THERMALLY INSULATED PHASE CHANGE MATERIAL MEMORY CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 05-24-2012 |
20120129313 | THERMALLY INSULATED PHASE MATERIAL CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 05-24-2012 |
20120202333 | METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS - A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided. | 08-09-2012 |
20120276688 | METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS - A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided. | 11-01-2012 |
20120280197 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 11-08-2012 |
20120299136 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 11-29-2012 |
20120318649 | Silicide Micromechanical Device and Methods to Fabricate Same - A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a silicon layer disposed over an insulating layer that is disposed on a silicon substrate; releasing a portion of the silicon layer from the insulating layer so that it is at least partially suspended over a cavity in the insulating layer; depositing a metal (e.g., Pt) on at least one surface of at least the released portion of the silicon layer and, using a thermal process, fully siliciding at least the released portion of the silicon layer using the deposited metal. The method eliminates silicide-induced stress to the released Si member, as the entire Si member is silicided. Furthermore no conventional wet chemical etch is used after forming the fully silicided material thereby reducing a possibility of causing corrosion of the silicide and an increase in stiction. | 12-20-2012 |
20130001500 | PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR - A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material. | 01-03-2013 |
20130005053 | Magnetic Spin Shift Register Memory - A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material. | 01-03-2013 |
20130020183 | Silicide Micromechanical Device and Methods to Fabricate Same - A miniaturized electro-mechanical switch includes a moveable portion having a contact configured to make, when the switch is actuated, an electrical connection between two stationary points. At least the contact is composed of a fully silicided material. A structure includes a silicon layer formed over an insulator layer and a micromechanical switch formed at least partially within the silicon layer. The micromechanical switch has a conductive structure, and where at least electrically contacting portions of the conductive structure are comprised of fully silicided material. | 01-24-2013 |
20130087756 | HEAT SHIELD LINER IN A PHASE CHANGE MEMORY CELL - A memory cell structure and method to form such structure. An example memory cell includes a bottom electrode formed within a substrate. The memory cell also includes a phase change memory element in contact with the bottom electrode. The memory cell includes a liner laterally surrounding the phase change memory element. The liner includes dielectric material that is thermally conductive and electrically insulating. The memory cell includes an insulating dielectric layer laterally surrounding the liner. The insulating dielectric layer includes material having a lower thermal conductivity than that of the liner. | 04-11-2013 |
20130087860 | BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS - Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions. | 04-11-2013 |
20130105947 | HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE | 05-02-2013 |
20130234260 | INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN - The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask. | 09-12-2013 |
20130299768 | THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS - Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material. | 11-14-2013 |
20130328173 | HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE - A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved. | 12-12-2013 |
20140124870 | SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS - One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines. | 05-08-2014 |
20140124935 | SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS - One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have line widths of less than forty nanometers. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, performing a first sputter etch of the layer of conductive metal using a methanol plasma, and performing a second sputter etch of the layer of conductive metal using a second plasma, wherein a portion of the layer of conductive metal that remains after the second sputter etch forms the one or more conductive lines. | 05-08-2014 |
20140127906 | SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS - Fabricating conductive lines in an integrated circuit includes providing a conductive metal in a multi-layer structure, performing a first sputter etch of the conductive metal using methanol plasma, and performing a second sputter etch of the conductive metal using a second plasma, wherein a portion of the conductive metal that remains after the second sputter etch forms the conductive lines. Alternatively, fabricating conductive lines includes providing a conductive metal as an intermediate layer in a multi-layer structure, etching the multi-layer structure to expose the conductive metal, performing a first etch of the conductive metal using methanol plasma, performing a second sputter etch of the conductive metal using a second plasma, wherein a portion of the conductive metal that remains after the second sputter etch forms the conductive lines, forming a liner that surrounds the conductive lines, and depositing a dielectric layer on the multi-layer structure. | 05-08-2014 |
20140154862 | UNIFORM CRITICAL DIMENSION SIZE PORE FOR PCRAM APPLICATION - A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material. | 06-05-2014 |
20140159227 | PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS - Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. | 06-12-2014 |
20140159242 | PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS - An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer line widths, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers. | 06-12-2014 |
20140166967 | SMALL FOOTPRINT PHASE CHANGE MEMORY CELL - An example embodiment disclosed is a phase change memory cell in a semiconductor wafer. The semiconductor wafer includes a first metalization layer (Metal 1). The phase change memory cell includes an insulating substrate defining a non-sublithographic via. The non-sublithographic via is located on the first metalization layer and includes a bottom and a sidewall. Intermediate insulating material is positioned below the insulating substrate. The intermediate insulating material defines a sublithographic aperture passing through the bottom of the non-sublithographic via. A bottom electrode is positioned within the sublithographic aperture, and is composed of conductive non-phase change material. The non-sublithographic via includes phase change material positioned within. The phase change material is electrically coupled to the bottom electrode. A liner is positioned along the sidewall of the non-sublithographic via. The liner is electrically coupled to the phase change material and is composed of the conductive non-phase change material. | 06-19-2014 |
20140183667 | NANOPORE SENSOR DEVICE - A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed. A dielectric spacer and a conformal conductive layer are subsequently formed. Peripheral electrodes laterally spaced from the electrode line are formed by pattering the conformal conductive layer. After deposition of a second dielectric material layer that encapsulates the template structure, the template structure is removed to provide a cavity that passes through the pair of electrode plates, the electrode line, and the peripheral electrodes. A nanoscale sensor thus formed can electrically characterize a nanoscale string by passing the nanoscale string through the cavity while electrical measurements are performed employing the various electrodes. | 07-03-2014 |
20140183668 | NANOPORE SENSOR DEVICE - A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed. A dielectric spacer and a conformal conductive layer are subsequently formed. Peripheral electrodes laterally spaced from the electrode line are formed by pattering the conformal conductive layer. After deposition of a second dielectric material layer that encapsulates the template structure, the template structure is removed to provide a cavity that passes through the pair of electrode plates, the electrode line, and the peripheral electrodes. A nanoscale sensor thus formed can electrically characterize a nanoscale string by passing the nanoscale string through the cavity while electrical measurements are performed employing the various electrodes. | 07-03-2014 |
20140191371 | Catalytic Etch With Magnetic Direction Control - A material can be locally etched with arbitrary changes in the direction of the etch. A ferromagnetic-material-including catalytic particle is employed to etch the material. A wet etch chemical or a plasma condition can be employed in conjunction with the ferromagnetic-material-including catalytic particle to etch a material through a catalytic reaction between the catalytic particle and the material. During a catalytic etch process, a magnetic field is applied to the ferromagnetic-material-including catalytic particle to direct the movement of the particle to any direction, which is chosen so as to form a contiguous cavity having at least two cavity portions having different directions. The direction of the magnetic field can be controlled so as to form the contiguous cavity in a preplanned pattern, and each segment of the contiguous cavity can extend along an arbitrary direction. | 07-10-2014 |
20140252629 | Self-Aligned Pitch Split for Unidirectional Metal Wiring - Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided. | 09-11-2014 |
20140252630 | Self-Aligned Pitch Split For Unidirectional Metal Wiring - Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided. | 09-11-2014 |
20140264861 | SPUTTER ETCH PROCESSING FOR HEAVY METAL PATTERNING IN INTEGRATED CIRCUITS - A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of first hard mask layer using a chlorine-based plasma or a sulfur fluoride-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma, wherein a portion of the layer of copper containing conductive metal residing below a portion of the first hard mask layer that remains after the second sputter etch forms the one or more conductive lines. In one embodiment, the second plasma is a fluorocarbon-based plasma. | 09-18-2014 |
20140273437 | SUBTRACTIVE PLASMA ETCHING OF A BLANKET LAYER OF METAL OR METAL ALLOY - A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch. | 09-18-2014 |
20140329351 | FABRICATING A SMALL-SCALE RADIATION DETECTOR - A method for a constructing radiation detector includes fabricating a multi-layer structure upon a wafer, the multi-layer structure comprising a plurality of metal layers, a plurality of sacrificial layers, and a plurality of insulating layers, forming a cavity within the multi-layer structure, filling the cavity with a gas that ionizes in response to nuclear radiation, and sealing the gas within the cavity. | 11-06-2014 |
20150044426 | CATALYTIC ETCH WITH MAGNETIC DIRECTION CONTROL - A material can be locally etched with arbitrary changes in the direction of the etch. A ferromagnetic-material-including catalytic particle is employed to etch the material. A wet etch chemical or a plasma condition can be employed in conjunction with the ferromagnetic-material-including catalytic particle to etch a material through a catalytic reaction between the catalytic particle and the material. During a catalytic etch process, a magnetic field is applied to the ferromagnetic-material-including catalytic particle to direct the movement of the particle to any direction, which is chosen so as to form a contiguous cavity having at least two cavity portions having different directions. The direction of the magnetic field can be controlled so as to form the contiguous cavity in a preplanned pattern, and each segment of the contiguous cavity can extend along an arbitrary direction. | 02-12-2015 |