Patent application number | Description | Published |
20110228781 | Combined Hardware/Software Forwarding Mechanism and Method - A forwarding system comprises a identification engine, a hardware forwarding engine configured to process an ingressing packet, a software forwarding engine configured to process the ingressing packet, and a selection engine. The selection engine is configured to select one of the hardware forwarding engine or the software forwarding engine to process the ingressing packet. The selection is based on at least one of an indication of resource availability or a classification of the ingressing packet based on a priority of a flow as determined by the identification engine. In some embodiments, the selection engine selects different forwarding engines to process different packets of a same flow based on changes in resource availability or classification of the ingressing packet. | 09-22-2011 |
20110229131 | VERSATILE OPTICAL NETWORK INTERFACE METHODS AND SYSTEMS - Methods and systems for implementing versatile optical terminals that detect optical transmission protocols and subsequently adapt to the correct protocol are disclosed. In an embodiment, an interface device for providing an interface for a first network with a passive optical network (PON) is disclosed. The interface device includes a protocol detection circuit for determining whether optical communication signals received from the PON conform to a first optical communication protocol, and a switchover control circuit that reconfigures the interface device to work with a second optical communication protocol when the received optical communication signals do not conform to the first optical communication protocol. | 09-22-2011 |
20120036415 | Systems and Methods for Performing Forward Error Correction - In accordance with the teachings described herein, systems and methods are provided for performing forward error correction. A decoder for performing forward error correction for a frame in a data stream includes a state machine configured to determine if a code block within the frame received by the decoder is a complete code block or a partial code block, the frame including a plurality of code blocks. A decoding unit is configured to receive the code block, and, when the code block is a partial code block, to generate an output based on decoding the partial code block and an additional partial decoding result that is input to the decoding unit. | 02-09-2012 |
20140133854 | VERSATILE OPTICAL NETWORK INTERFACE METHODS AND SYSTEMS - Methods and systems for implementing versatile optical terminals that detect optical transmission protocols and subsequently adapt to the correct protocol are disclosed. In an embodiment, an interface device for providing an interface for a first network with a passive optical network (PON) is disclosed. The interface device includes a protocol detection circuit for determining whether optical communication signals received from the PON conform to a first optical communication protocol, and a switchover control circuit that reconfigures the interface device to work with a second optical communication protocol when the received optical communication signals do not conform to the first optical communication protocol. | 05-15-2014 |
20140310439 | LOW LATENCY INTERRUPT WITH EXISTENCE OF INTERRUPT MODERATION - A method for generating interrupt requests, the method comprising: receiving, by a first circuit, an indication of an occurrence of an interrupt triggering event; determining whether a time difference between the occurrence of the interrupt triggering event and an occurrence of a last interrupt triggering event that preceded the occurrence of the interrupt triggering event exceeded a threshold; generating, by the first circuit, an interrupt request in response to the occurrence of the interrupt triggering event if the time difference exceeded the threshold; and delaying, for a predetermined delay period after a generation of a last interrupt request, a generating of the interrupt request that is responsive to the occurrence of the interrupt triggering event if the time difference is shorter than the threshold. | 10-16-2014 |
20150016451 | COMBINED HARDWARE/SOFTWARE FORWARDING MECHANISM AND METHOD - A forwarding system comprises a identification engine, a hardware forwarding engine configured to process an ingressing packet, a software forwarding engine configured to process the ingressing packet, and a selection engine. The selection engine is configured to select one of the hardware forwarding engine or the software forwarding engine to process the ingressing packet. The selection is based on at least one of an indication of resource availability or a classification of the ingressing packet based on a priority of a flow as determined by the identification engine. In some embodiments, the selection engine selects different forwarding engines to process different packets of a same flow based on changes in resource availability or classification of the ingressing packet. | 01-15-2015 |
20150081726 | CONFIGURABLE PARSER AND A METHOD FOR PARSING INFORMATION UNITS - A system that includes a first interleaved sequence of configurable parsing engines and concatenating modules. Each parsing engine is followed by a concatenating module. The first interleaved sequence is arranged to process an information unit. Different portions of the information unit are processed by different configurable parsing engines. At least one configurable parsing engine is arranged to (a) process of a portion of the information unit in response to a previous processing result provided from a previous configurable parting engine; and to (b) generate a current processing result to be used by a next configurable parsing engine. | 03-19-2015 |
20150120855 | HYBRID REMOTE DIRECT MEMORY ACCESS - A method for hybrid RDMA, the method may include: (i) receiving, by a first computer, a packet that was sent over a network from a second computer; wherein the packet may include data and metadata; (ii) determining, in response to the metadata, whether the data should be (a) directly written to a first application memory of the first computer by a first hardware accelerator of the first computer; or (b) indirectly written to the first application memory; (iii) indirectly writing or indirectly writing in response to the determination. | 04-30-2015 |