Patent application number | Description | Published |
20090141424 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via. | 06-04-2009 |
20090194850 | Crack Stops for Semiconductor Devices - Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions. | 08-06-2009 |
20090200675 | Passivated Copper Chip Pads - A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels. | 08-13-2009 |
20090201043 | Crack Sensors for Semiconductor Devices - Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure. | 08-13-2009 |
20090203192 | Crack Stop Trenches - Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels. | 08-13-2009 |
20090239375 | Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 09-24-2009 |
20100022085 | Method of Forming Support Structures for Semiconductor Devices - Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials. | 01-28-2010 |
20100314619 | Test Structures and Methods for Semiconductor Devices - Test structures for semiconductor devices, methods of forming test structures, semiconductor devices, methods of manufacturing thereof, and testing methods for semiconductor devices are disclosed. In one embodiment, a test structure for a semiconductor device includes at least one first contact pad disposed in a first material layer in a scribe line region of the semiconductor device. The at least one first contact pad has a first width. The test structure also includes at least one second contact pad disposed in a second material layer proximate the at least one first contact pad in the first material layer. The at least one second contact pad has a second width that is greater than the first width. | 12-16-2010 |
20110074033 | Crack Stop Trenches - Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels. | 03-31-2011 |
20110244658 | Crack Stops for Semiconductor Devices - Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions. | 10-06-2011 |
20120025382 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 02-02-2012 |
20120074536 | Methods of Manufacturing Semiconductor Devices and Structures Thereof - Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern. | 03-29-2012 |
20120099243 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via. | 04-26-2012 |
20120104622 | Through Level Vias and Methods of Formation Thereof - In one embodiment, a semiconductor device includes a first metal line disposed in a first metal level above a substrate. A second metal line is disposed in a second metal level disposed over the first metal level. A third metal line is disposed in a third metal level disposed over the second metal level. A through level via contacts the first metal line and the third metal line. | 05-03-2012 |
20130224946 | Passivated Copper Chip Pads - A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels. | 08-29-2013 |
20140118020 | STRUCTURES AND METHODS FOR DETERMINING TDDB RELIABILITY AT REDUCED SPACINGS USING THE STRUCTURES - A structure for TDDB measurement, a method determining TDDB at reduced spacings. The structure includes an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first wire formed in the lower dielectric layer; a second wire formed in the upper dielectric layer; and wherein a distance between the first wire and the second wire measured in a direction parallel to the interface is below the lithographic resolution limit of the fabrication technology. | 05-01-2014 |
20140203436 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis. | 07-24-2014 |
20140210040 | ELECTRONIC FUSE LINE WITH MODIFIED CAP - An electronic fuse structure having an M | 07-31-2014 |
20140217612 | ELECTRONIC FUSE HAVING A DAMAGED REGION - An electronic fuse structure including an M | 08-07-2014 |
20140332923 | E-FUSE WITH HYBRID METALLIZATION - An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor. The first conductor has a higher resistance to electromigration than the second conductor. The first region and the second region have a common width. The length of the first region is longer than the length of the second region. | 11-13-2014 |
20140332963 | INTERCONNECT WITH HYBRID METALLIZATION - An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level. | 11-13-2014 |
20150021736 | ELECTRONIC FUSE LINE WITH MODIFIED CAP - An electronic fuse structure having an M | 01-22-2015 |
20150028484 | RANDOM LOCAL METAL CAP LAYER FORMATION FOR IMPROVED INTEGRATED CIRCUIT RELIABILITY - A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier. | 01-29-2015 |
20150035556 | Crack Sensors for Semiconductor Devices - Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure. | 02-05-2015 |
20150069609 | 3D CHIP CRACKSTOP - Embodiments of the present invention provide a crackstop and seal ring for 3D chip stacked wafers. A continuous through-silicon trench (TST) spans multiple wafers of a 3D chip stacked wafer, and forms a closed shape around a functional circuit or die, protecting the chip during subsequent fabrication such as dicing and packaging. | 03-12-2015 |
20150084196 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 03-26-2015 |