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| 20120104443 | IIIOxNy ON SINGLE CRYSTAL SOI SUBSTRATE AND III n GROWTH PLATFORM - A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIO | 05-03-2012 |
| 20120104567 | IIIOxNy ON REO/Si - An insulative layer on a semiconductor substrate and a method of fabricating the structure includes the steps of depositing a single crystal layer of rare earth oxide on a semiconductor substrate to provide electrical insulation and thermal management. The rare earth oxide is crystal lattice matched to the substrate. A layer of single crystal IIIO | 05-03-2012 |
| 20120241890 | IR SENSOR USING REO UP-CONVERSION - A pumped sensor system includes a substrate with a first layer formed thereon and doped for a first type conduction and a second layer doped for a second type conduction, whereby the first and second layers form a silicon light detector at an up-conversion wavelength. A ternary rare earth oxide is formed on the second layer and crystal lattice matched to the second layer. The oxide is a crystalline bulk oxide with a controlled percentage of an up-conversion component and a majority component. The majority component is insensitive to any of pump, sense, or up-conversion wavelengths and the up-conversion component is selected to produce energy at the up-conversion wavelength in response to receiving energy at the pump and sense wavelengths. The layer of oxide defines a light input area sensitive to a pump wavelength and a light input area sensitive to a sense wavelength. | 09-27-2012 |
| 20120280276 | Single Crystal Ge On Si - A single crystal germanium-on-silicon structure includes a single crystal silicon substrate. A single crystal layer of gadolinium oxide is epitaxially grown on the substrate. The gadolinium oxide has a cubic crystal structure and a lattice spacing approximately equal to the lattice spacing or a multiple of the single crystal silicon. A single crystal layer of lanthanum oxide is epitaxially grown on the gadolinium oxide with a thickness of approximately 12 nm or less. The lanthanum oxide has a lattice spacing approximately equal to the lattice spacing or a multiple of single crystal germanium and a cubic crystal structure approximately similar to the cubic crystal structure of the gadolinium oxide. A single crystal layer of germanium with a (111) crystal orientation is epitaxially grown on the layer of lanthanum oxide. | 11-08-2012 |
| 20130032858 | RARE EARTH OXY-NITRIDE BUFFERED III-N ON SILICON - Rare earth oxy-nitride buffered III-N on silicon includes a silicon substrate with a rare earth oxide (REO) structure, including several REO layers, is deposited on the silicon substrate. A layer of single crystal rare earth oxy-nitride is deposited on the REO structure. The REO structure is stress engineered to approximately crystal lattice match the layer of rare earth oxy-nitride so as to provide a predetermined amount of stress in the layer of rare earth oxy-nitride. A III oxy-nitride structure, including several layers of single crystal rare earth oxy-nitride, is deposited on the layer of rare earth oxy-nitride. A layer of single crystal III-N nitride is deposited on the III oxy-nitride structure. The III oxy-nitride structure is chemically engineered to approximately crystal lattice match the layer of III-N nitride and to transfer the predetermined amount of stress in the layer of rare earth oxy-nitride to the layer of III-N nitride. | 02-07-2013 |
| 20130069039 | Ge QUANTUM DOTS FOR DISLOCATION ENGINEERING OF III-N ON SILICON - A virtual substrate structure includes a crystalline silicon substrate with a first layer of III-N grown on the silicon substrate. Ge clusters or quantum dots are grown on the first layer of III-N and a second layer of III-N is grown on the Ge clusters or quantum dots and any portions of the first layer of III-N exposed between the Ge clusters or quantum dots. Additional alternating Ge clusters or quantum dots and layers of III-N are grown on the second layer of III-N forming an upper surface of III-N. Generally, the additional alternating layers of Ge clusters or quantum dots and layers of III-N are continued until dislocations in the III-N adjacent the upper surface are substantially eliminated. | 03-21-2013 |
| 20130099357 | STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON - A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer. | 04-25-2013 |
| 20130214282 | III-N ON SILICON USING NANO STRUCTURED INTERFACE LAYER - A method of fabricating a layer of single crystal semiconductor material on a silicon substrate including providing a crystalline silicon substrate and epitaxially depositing a nano structured interface layer on the substrate. The nano structured interface layer has a thickness up to a critical thickness. The method further includes epitaxially depositing a layer of single crystal semiconductor material in overlying relationship to the nano structured interface layer. Preferably, the method includes the nano structured interface layer being a layer of coherently strained nano dots of selected material. The critical thickness of the nano dots includes a thickness up to a thickness at which the nano dots become incoherent. | 08-22-2013 |
| 20130248853 | NUCLEATION OF III-N ON REO TEMPLATES - A method of fabricating a layer of single crystal III-N material on a silicon substrate includes epitaxially growing a REO template on a silicon substrate. The template includes a REO layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate and selected to protect the substrate from nitridation. Either a rare earth oxynitride or a rare earth nitride is formed adjacent the upper surface of the template and a layer of single crystal III-N material is epitaxially grown thereon. | 09-26-2013 |
| 20140167057 | REO/ALO/AlN TEMPLATE FOR III-N MATERIAL GROWTH ON SILICON - A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide. | 06-19-2014 |
| 20140231817 | III-N MATERIAL GROWN ON ALO/ALN BUFFER ON SI SUBSTRATE - III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. | 08-21-2014 |
| 20140231818 | AlN CAP GROWN ON GaN/REO/SILICON SUBSTRATE STRUCTURE - III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer. | 08-21-2014 |
| 20140239307 | REO GATE DIELECTRIC FOR III-N DEVICE ON Si SUBSTRATE - A rare earth oxide gate dielectric on III-N material grown on a silicon substrate includes a single crystal stress compensating template positioned on a silicon substrate. The stress compensating template is substantially crystal lattice matched to the surface of the silicon substrate. A GaN structure is positioned on the surface of the stress compensating template and substantially crystal lattice matched thereto. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched thereto. A single crystal rare earth oxide dielectric layer is grown on the active layer of III-N material. | 08-28-2014 |
| 20140246679 | III-N MATERIAL GROWN ON ErAlN BUFFER ON Si SUBSTRATE - III-N material grown on a buffer on a silicon substrate includes a single crystal electrically insulating buffer positioned on a silicon substrate. The single crystal buffer includes rare earth aluminum nitride substantially crystal lattice matched to the surface of the silicon substrate, i.e. a lattice co-incidence between REAlN and Si better than a 5:4 ratio. A layer of single crystal III-N material is positioned on the surface of the buffer and substantially crystal lattice matched to the surface of the buffer. | 09-04-2014 |
| 20150014676 | III-N MATERIAL GROWN ON REN EPITAXIAL BUFFER ON Si SUBSTRATE - A method of growing III-N material on a silicon substrate includes the steps of epitaxially growing a single crystal rare earth oxide on a silicon substrate, epitaxially growing a single crystal rare earth nitride on the single crystal rare earth oxide, and epitaxially growing a layer of single crystal III-N material on the single crystal rare earth nitride. | 01-15-2015 |
| 20150069409 | HETEROSTRUCTURE WITH CARRIER CONCENTRATION ENHANCED BY SINGLE CRYSTAL REO INDUCED STRAINS - A heterostructure grown on a silicon substrate includes a single crystal rare earth oxide template positioned on a silicon substrate, the template being substantially crystal lattice matched to the surface of the silicon substrate. A heterostructure is positioned on the template and defines at least one heterojunction at an interface between a III-N layer and a III-III-N layer. The template and the heterostructure are crystal matched to induce an engineered predetermined tensile strain at the at least one heterojunction. A single crystal rare earth oxide dielectric layer is grown on the heterostructure so as to induce an engineered predetermined compressive stress in the single crystal rare earth oxide dielectric layer and a tensile strain in the III-III-N layer. The tensile strain in the III-III-N layer and the compressive stress in the REO layer combining to induce a piezoelectric field leading to higher carrier concentration in 2DEG at the heterojunction. | 03-12-2015 |
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| 20140245237 | HYBRID EVOLUTIONARY ALGORITHM FOR TRIPLE-PATTERNING - According to one embodiment of the present invention, a computer-implemented method for validating a design includes generating, using the computer, a first graph representative of the design, when the computer is invoked to validate the design, and decompose, using the computer, the first graph into at least three sets using a hybrid evolutionary algorithm to form a colored graph. | 08-28-2014 |
| 20150052490 | DETECTING AND DISPLAYING MULTI-PATTERNING FIX GUIDANCE - A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable. | 02-19-2015 |
| Patent application number | Description | Published |
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| 20090276432 | DATA FILE STORING MULTIPLE DATA TYPES WITH CONTROLLED DATA ACCESS - A method and apparatus for efficiently storing multiple data types in a computer's register or data file. A single data file can store data with a variety of sizes and number formats, including integers, fractions, and mixed numbers. The register file is partitioned into fields, such that only the relevant portions of the register file are read or written. | 11-05-2009 |
| 20100122068 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 05-13-2010 |
| 20100199073 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 08-05-2010 |
| 20100199075 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 08-05-2010 |
| 20120096243 | MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD - A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines. | 04-19-2012 |
