| Patent application number | Description | Published |
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| 20130117506 | INTEGRATED CIRCUIT DEVICE, DATA STORAGE ARRAY SYSTEM AND METHOD THEREFOR - An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command. | 05-09-2013 |
| 20140298111 | CONTROLLER, SATA SYSTEM AND METHOD OF OPERATION THEREFOR - A controller for operably coupling a drive unit to a host unit in a serial advanced technology attachment (SATA) system is described. The controller comprises a hardware processor arranged to: receive a plurality of SATA data frames; identify a first primitive sequence in at least one of the plurality of SATA data frames that adversely affects a performance of the SATA system; and replace the identified first primitive sequence with a second primitive sequence in response thereto. | 10-02-2014 |
| 20150234419 | METHODS AND APPARATUS FOR ADAPTIVE TIME KEEPING FOR MULTIPLE TIMERS - A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data. | 08-20-2015 |
| 20150242343 | SYSTEM ON CHIP AND METHOD OF OPERATING A SYSTEM ON CHIP - A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers. | 08-27-2015 |
| 20150378730 | SYSTEM ON A CHIP WITH MANAGING PROCESSOR AND METHOD THEREFOR - A system on a chip comprises a managing processor for controlling operations of the system on a chip. The managing processor comprises a core monitor control logic circuit operable to: receive at least one instruction; determine whether the instruction is an activation instruction; determine whether the managing processor is in or transitioning to an idle state; and transition the managing processor from a first mode of operation to a second mode of operation in response to the instruction being an activation instruction and the managing processor being in or transitioning to an idle state. | 12-31-2015 |
| 20150379276 | SYSTEM ON A CHIP, CONTROLLER AND METHOD FOR SECURING DATA - A system on a chip for securing data is described. The system on a chip comprises: a controller arranged to: partition a data block into a plurality of segments; and determine and extract a subset of the plurality of segments to be compressed. A compressor logic circuit is arranged to receive and compress the subset of the plurality of segments. The controller is arranged to retrieve the compressed subset of the plurality of segments from the compressor logic circuit and attach the compressed subset of the plurality of segments to a remainder of the partitioned data block for transmission. | 12-31-2015 |
| 20160004274 | APPARATUS, A METHOD AND MACHINE READABLE INSTRUCTIONS FOR QUERYING TIMERS - An apparatus including: an input interface configured to enable user configuration of a future time window; and a report interface configured to produce a report relating to a first sub-set of a plurality of active timers that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers expire during the user-configured future time window. | 01-07-2016 |
| 20160100367 | POWER MANAGEMENT MODULE AND METHOD THEREFOR - A power management module comprising a client monitoring component arranged to monitor idle periods for a client component, and derive at least one idle period characteristic value for the client component based at least partly on the monitoring of the idle periods therefore. The power management module further comprises a power mode control component arranged to receive an indication of the client component entering an idle state, cause the client component to be put into a reduced power mode upon expiry of a first period of time, and cause the client component to be brought out of the reduced power mode upon expiry of a second period of time. At least one of the first and second periods of time is configured based at least partly on the idle period characteristic value(s) derived by the client monitoring component for the client component. | 04-07-2016 |
| 20160103769 | PROCESSING DEVICE AND METHOD THEREOF - A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral. | 04-14-2016 |
| 20160110275 | METHOD AND APPARATUS FOR OFFLOADING FUNCTIONAL DATA FROM AN INTERCONNECT COMPONENT - An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data. | 04-21-2016 |
