| Patent application number | Description | Published |
|---|
| 20090055780 | Simultaneous Power and Timing Optimization in Integrated Circuits by Performing Discrete Actions on Circuit Components - A graph-based iterative method is provided for selecting component modifications in an integrated circuit design that reduce the power consumption to a minimum while still meeting timing constraints. Channel-connected components are represented as nodes in a timing graph and edges in the timing graph represent directed paths. From the timing graph, a move graph is constructed containing a plurality of move nodes. Each move node represents a change to one of the components in one of the timing graph nodes. A given timing graph node can result in a plurality of move nodes. Move nodes can be merged into group nodes, and both the move nodes and group nodes are assigned a weight based on the change in power and timing effects of the associated components changes. These weights are used to select move nodes or group nodes. In general, a set of move or group nodes is selected representing the maximum cumulative weight and the components changes associated with the nodes in the set are performed on the integrated circuit design. Moves that cause timing violations are reversed. The node weights are updated following components changes and the selection of node sets is repeated iteratively until the power consumption converges to a minimum. | 02-26-2009 |
| 20090192776 | CHARGE-BASED CIRCUIT ANALYSIS - A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions. | 07-30-2009 |
| 20100262412 | INTEGRATED CIRCUIT MODELING BASED ON EMPIRICAL TEST DATA - In accordance with one embodiment, a plurality of empirical measurements of a fabricated integrated circuit including a fabricated transistor having multiple terminals is received. The plurality of empirical measurements each include an empirical terminal current set and an empirical terminal voltage set for the terminals of the fabricated transistor. A mathematical simulation model of a simulated transistor is also received. Utilizing the mathematical simulation model, an intermediate data set is calculated by determining, for each of a plurality of different terminal voltage sets, a simulated terminal current set and a simulated terminal charge set. A modeling tool processes the intermediate data set to obtain a time domain simulation model of the fabricated transistor that, for each of the plurality of empirical measurements, provides a simulated terminal charge set. The time domain simulation model is stored in a computer-readable data storage medium. | 10-14-2010 |
| 20100262413 | COMPENSATING FOR VARIATIONS IN DEVICE CHARACTERISTICS IN INTEGRATED CIRCUIT SIMULATION - According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium. | 10-14-2010 |
| 20120260117 | Dynamically Tune Power Proxy Architectures - A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted. | 10-11-2012 |
| 20130320340 | CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS - A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed. | 12-05-2013 |
| 20140007030 | INTEGRATED DESIGN ENVIRONMENT FOR NANOPHOTONICS | 01-02-2014 |
| 20140007032 | INTEGRATED DESIGN ENVIRONMENT FOR NANOPHOTONICS | 01-02-2014 |
| 20150066467 | POWER AND PERFORMANCE SORTING OF MICROPROCESSORS FROM FIRST INTERCONNECT LAYER TO WAFER FINAL TEST - A system, method and computer program product for sorting Integrated Circuits (chips), particularly microprocessor chips, and particularly that predicts chip performance or power for sorting purposes. The system and method described herein uses a combination of performance-predicting parameters that are measured early in the process, and applies a unique method to project where the part, e.g., microprocessor IC, will eventually be sorted. Sorting includes classifying the IC product to a subset of a family of products with the product satisfying certain performance characteristics or specifications, in the early stages of manufacturing, e.g., before the end product is fully fabricated. | 03-05-2015 |
