Patent application number | Description | Published |
20130021016 | BANDGAP REFERENCE CIRCUIT AND METHOD OF STARTING BANDGAP REFERENCE CIRCUIT - In accordance with a bandgap circuit and a method of starting the bandgap circuit, a start signal is continuously supplied to a differential amplifier circuit to start up the differential amplifier circuit that controls a bandgap core circuit until the differential amplifier circuit has started up, and then the supply of the start signal to the differential amplifier circuit is discontinued after the differential amplifier circuit has started up. | 01-24-2013 |
20130026652 | SEMICONDUCTOR DEVICE - A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip | 01-31-2013 |
20130039112 | SEMICONDUCTOR DEVICE - In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other. | 02-14-2013 |
20130039118 | SEMICONDUCTOR MEMORY DEVICE HAVING DIODE CELL STRUCTURE - A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell. | 02-14-2013 |
20130039136 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled in series between the second bit line and a first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and supply a control signal to a gate of the second transistor. | 02-14-2013 |
20130043596 | SEMICONDUCTOR DEVICE - A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern. | 02-21-2013 |
20130045582 | CAPACITOR INSULATING FILM, METHOD OF FORMING THE SAME, CAPACITOR AND SEMICONDUCTOR DEVICE USING THE CAPACITOR INSULATING FILM - A capacitor insulating film may include, but is not limited to, strontium, titanium, and oxygen. The capacitor insulating film has a ratio of a spectrum intensity of ( | 02-21-2013 |
20130056851 | Molybdenum Oxide Top Electrode for DRAM Capacitors - A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO | 03-07-2013 |
20130058180 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A system includes a first circuit and a second circuit that are constituted by a semiconductor device, the second circuit controlling the first circuit. The first circuit includes an interface unit that performs communication with the second circuit, a plurality of sense amplifiers including a first sense amplifier, each of the plurality of sense amplifiers performing communication with the interface unit, a first global bit line, a dummy global bit line, a plurality of first memory blocks, each of the first memory blocks including a first hierarchy switch that is connected to the first global bit line, a dummy memory block including a dummy hierarchy switch that is connected to the dummy global bit line, and a first dummy local bit line connected to the dummy global bit line, and a control circuit that controls the first hierarchy switches and the dummy hierarchy switch. | 03-07-2013 |
20130069202 | Electrode Treatments for Enhanced DRAM Performance - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO | 03-21-2013 |
20130071991 | Electrode Treatments for Enhanced DRAM Performance - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO | 03-21-2013 |
20130075813 | SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first semiconductor structure is formed, which extends upwardly in a direction perpendicular to a main surface from a surface of a semiconductor substrate. A first insulating film is formed which extends on a surface of the first semiconductor structure. A gate electrode is formed which extends on the first insulating film. The gate electrode has a top surface which is lower than a top surface of the first semiconductor structure. A liner film is formed, which may include, but is not limited to, first and second liner portions. The first liner portion covers the gate electrode. The second liner portion extends upwardly from the top surface of the gate electrode. The liner film includes nitrogen and oxygen. | 03-28-2013 |
20130080826 | SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE - Disclosed herein is a semiconductor device that includes a verification circuit and an error processing circuit. the verification circuit verifies second bits of an external command to generate the verification result signal. The error processing circuit supplies a follow-up signal to a bank control circuit after a lapse of a first period and a second period when the verification result signal indicates a fail state during a write operation. The first period corresponds to a write latency indicating a period between when a write command is generated and when a data associated with the write command is supplied from outside. The second period corresponds to a write recovery latency indicating a period between when the bank control circuit issues a write execution signal to start writing the data to memory cells and when the write operation is completed. | 03-28-2013 |
20130082382 | SEMICONDUCTOR DEVICE - First and second sub-bumps are provided on both surfaces of each substrate along with a usual bump structure (first and second main bumps), and at least one of the first and second sub-bumps is made greater in height than the first and second main bumps, so that the sub-bumps come into contact with one another earlier than the main bumps at the time of joining semiconductor chips, thereby securing margins of joint among the main bumps and suppressing the thin-filming of a layer, such as a solder layer, to be fluidized by heating. | 04-04-2013 |
20130082404 | SEMICONDUCTOR DEVICE AND MEMORY SYSTEM - A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region. | 04-04-2013 |
20130082735 | LOGIC CIRCUIT PERFORMING EXCLUSIVE OR OPERATION AND DATA PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a logic circuit that includes a transistor T | 04-04-2013 |
20130082761 | SEMICONDUCTOR DEVICE HAVING INPUT RECEIVER CIRCUIT THAT OPERATES IN RESPONSE TO STROBE SIGNAL - Disclosed herein is a device that includes an input receiver circuit activated by a strobe signal to generate an output signal by comparing a potential of an input signal with a reference potential, and a noise canceller cancelling noise superimposed on the reference potential due to a change in the strobe signal. | 04-04-2013 |
20130088257 | SEMICONDUCTOR DEVICE HAVING IMPEDANCE CALIBRATION FUNCTION TO DATA OUTPUT BUFFER AND SEMICONDUCTOR MODULE HAVING THE SAME - Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit. | 04-11-2013 |
20130088258 | SEMICONDUCTOR DEVICE INCLUDING OUTPUT CIRCUIT CONSTITUTED OF PLURAL UNIT BUFFER CIRCUITS IN WHICH IMPEDANCE THEREOF ARE ADJUSTABLE - The semiconductor device comprises an output circuit that includes a plurality of unit buffer circuits each of which has an adjustable impedance, a control circuit that selectively activates one or ones of the unit buffer circuits, and an impedance adjustment unit that adjusts the impedances of the unit buffer circuits and includes a power line, a replica circuit, which has a replica impedance that is substantially equal to the adjustable impedance of each of the unit buffer circuits, and a load current generation circuit, which changes current flowing therethrough in accordance with the number of activated the one or ones of the unit buffer circuits. The replica circuit and the load current generation circuit are connected in common to the power line. | 04-11-2013 |
20130088911 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device includes a writing circuit and a reading circuit. The writing circuit executes a setting action for converting a resistance of a variable resistance element to a low resistance by applying current from one end side to the other end side of a memory cell via the variable resistance element, and a resetting action for converting the resistance to a high resistance by applying current from the other end side to the one end side via the variable resistance element. The reading circuit executes a first reading action for reading a resistance state of the variable resistance element by applying current from one end side to the other end side of the memory cell via the variable resistance element, and a second reading action for reading the resistance state by applying current from the other end side to the one end side via the variable resistance element. | 04-11-2013 |
20130089981 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention provides a method of manufacturing a semiconductor device, capable of forming, on a silicon layer, a nickel mono-silicide layer having a low resistance value and a desirable flatness. The method includes depositing a platinum-containing nickel layer that covers the silicon layer formed on the substrate, and that has crystallinity lower in a portion thereof close to the silicon layer than in a portion remote from the silicon layer, and forming a nickel mono-silicide layer at the interface between the silicon layer and the platinum-containing nickel layer by heating the substrate. | 04-11-2013 |
20130091327 | SEMICONDUCTOR DEVICE PERFORMING BURST ORDER CONTROL AND DATA BUS INVERSION - Disclosed herein is a device that a device including first data lines transmitting a plurality of sequential first data bits, respectively, second data lines transmitting a plurality of sequential second data bits, respectively, third data lines transmitting a plurality of sequential third data bits, respectively, a BOC circuit rearranging order of the plurality of first data bits supplied from the plurality of first data lines in accordance with address information, the BOC circuit supplying the resultant to the plurality of second data lines as the plurality of second data bits, and a DBI circuit performing inversion or non-inversion of the plurality of second data bits supplied from the plurality of second data lines independently of each other in accordance with a predetermined condition, the DBI circuit supplying the resultant to the plurality of third data lines as the plurality of third data bits. | 04-11-2013 |
20130093004 | SEMICONDUCTOR DEVICE INCLUDING DUMMY PILLAR NEAR INTERMEDIATE PORTION OF SEMICONDUCTOR PILLAR GROUP - A semiconductor device includes a semiconductor pillar group having semiconductor pillars which are formed in a first direction with a space left therebetween. A dummy pillar is disposed near a particular semiconductor pillar in the semiconductor pillar group in a second direction perpendicular to the first direction that is any one of the semiconductor pillars which are positioned in an intermediate portion exclusive of both end portions. Gate insulating films are formed on outer circumferential surfaces of the semiconductor pillars. One gate insulating film is formed on a part of an outer circumferential surface of the dummy pillar. Formed over side faces of the semiconductor pillars and over a side face of the dummy pillar via the gate insulating films, gate electrodes fill gaps between the semiconductor pillars and a gap between the particular semiconductor pillar and the dummy pillar. | 04-18-2013 |
20130093027 | LAYOUT DATA CREATION DEVICE FOR CREATING LAYOUT DATA OF PILLAR-TYPE TRANSISTOR - A layout data creation device includes a transistor adjustment unit. The transistor adjustment unit divides a pillar-type transistor including a plurality of unit pillar-type transistors into the unit pillar-type transistors groups. The unit pillar-type transistors can be placed in a placement area. The number of the unit pillar-type transistors in each group is an integer. The transistor adjustment unit generates sub-pillar-type transistors that are placed in the placement area. | 04-18-2013 |
20130093051 | Asymmetric MIM Capacitor for DRAM Devices - A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO | 04-18-2013 |
20130093083 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted. | 04-18-2013 |
20130093492 | DEVICE - A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit | 04-18-2013 |
20130094272 | DEVICE - A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit. | 04-18-2013 |
20130094321 | SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER TO CONTROL OUTPUT TIMING OF DATA AND DATA PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage. | 04-18-2013 |
20130095633 | METHODS OF MANUFACTURING VARIABLE RESISTANCE MEMORY AND SEMICONDUCTOR DEVICE - Disclosed herein a method of manufacturing a variable resistance memory, which comprises: forming a conductive plug on a substrate; forming a variable resistance film above the substrate, the variable resistance film covering a top surface of the conductive plug; forming an insulating interlayer above the substrate, the insulating interlayer covering a top surface of the conductive plug; forming a hole in the insulating interlayer by removing a part of the insulating interlayer disposed above the conductive plug; and forming a first electroconductive film in the hole extending from a top surface of the insulating interlayer so as to be in contact with the variable resistance film and to be electrically connected with the conductive plug via the variable resistance film. | 04-18-2013 |
20130097388 | DEVICE AND DATA PROCESSING SYSTEM - A device is disclosed which includes a register storing a plurality of latency data and a control unit responding to the latency data. Each of the latency data indicates a period of time between issue of a data transfer request command responsive to an access request from one of access request sources and initiation of a data transfer operation responsive to the data transfer request command. The control unit controls an order in issue of data transfer request commands responsive to access requests from the access request sources so that between issue of a first data transfer request command responsive to a first access request and initiation of a first data transfer operation responsive to the first data transfer request command, at least issue of a second data transfer request command responsive to a second access request is performed. | 04-18-2013 |
20130114364 | SEMICONDUCTOR DEVICE PERFORMING REFRESH OPERATION - Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal. | 05-09-2013 |
20130114366 | SEMICONDUCTOR DEVICE HAVING PLURAL SELECTION LINES SELECTED BASED ON ADDRESS SIGNAL - Disclosed herein is a device that includes: a set of address terminals supplied with a set of address signals, each of the address signals being changed in logic level; memory mats to which address ranges are allocated, respectively, the address ranges being different from each other, each of the memory mats including memory cells; and decoder units each provided correspondingly to corresponding memory mat. Each of the decoder units includes a set of first input nodes and a set of second input nodes, the set of first input nodes of each of the decoder units being coupled to the set of address terminals to receive the set of address signals, the set of second input nodes of each of the decoder units being coupled to receive an associated one of sets of control signals, each of the control signals being fixed in logic level. | 05-09-2013 |
20130117599 | SEMICONDUCTOR DEVICE OPERATING ACCORDING TO LATENCY VALUE - Disclosed herein is a device that includes a first register temporarily storing first information indicative of a reference latency, a second register temporarily storing second information indicative of an offset latency, a third register temporarily storing third information indicative of one of first and second operation modes, and a logic circuit configured to produce latency information in response to the first information when the third information is indicative of the first operation mode and to both of the first information and the second information when the third information is indicative of the second operation mode. | 05-09-2013 |
20130119512 | Top Electrode Templating for DRAM Capacitor - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer. | 05-16-2013 |
20130119513 | Adsorption Site Blocking Method for Co-Doping ALD Films - A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material. | 05-16-2013 |
20130119514 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes at least forming a lower electrode comprising titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide as a primary constituent on the lower electrode, forming a first protective film comprising a titanium compound on the dielectric film, and forming an upper electrode comprising titanium nitride on the first protective film. The method can include a step of forming a second protective film on the lower electrode before the step of forming the dielectric film on the lower electrode. | 05-16-2013 |
20130121091 | SYSTEM WITH CONTROLLER AND MEMORY - According to the system of the present invention, data (DQ) signals are outputted/received between a controller | 05-16-2013 |
20130121092 | SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED TO ONE ANOTHER - Disclosed herein is a device that includes a first semiconductor chip outputting a read command and a clock signal, a plurality of second semiconductor chips stacked to the first semiconductor chip, and a signal path electrically connected between the first and second semiconductor chips. Each of the second semiconductor chips performs a read operation to read out a data signal stored therein in response to the read command. Each of the second semiconductor chips includes a counter circuit performing a count operation in response to the clock signal to generate a count signal, and an output control circuit outputs the data signal to the signal path when the count signal indicates a predetermined value. The predetermined values of the second semiconductor chips are different from one another. | 05-16-2013 |
20130122683 | BLOCKING LAYERS FOR LEAKAGE CURRENT REDUCTION IN DRAM DEVICES - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. | 05-16-2013 |
20130126963 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having first and second regions, a first pillar transistor, and a second pillar transistor, wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar, wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar, wherein the first gate electrode is different in height from the second gate electrode, and the first and second pillar transistors form a CMOS device. | 05-23-2013 |
20130127048 | DEVICE - A device has a first substrate having a first surface; a first electrode pad arranged on the first surface of the first substrate; a first insulator film provided on the first surface of the first substrate so that the first electrode pad is exposed; a first bump electrode provided on the first electrode pad and having a first diameter; and a second bump electrode provided on the first insulator film and having a second diameter smaller than the first diameter. | 05-23-2013 |
20130132797 | CONTROL METHOD FOR A SEMICONDUCTOR MEMORY DEVICE - To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained. | 05-23-2013 |
20130134421 | SEMICONDUCTOR CHIP HAVING PLURAL PENETRATING ELECTRODES THAT PENETRATE THERETHROUGH - Disclosed herein is a semiconductor chip that includes: a semiconductor chip body including a semiconductor substrate and a circuit element layer provided on a main surface of the semiconductor substrate, the circuit element layer including a plurality of circuit elements; first to fourth penetrating electrodes penetrating the semiconductor chip body; a first conductive path electrically connected between the first penetrating electrode and the second penetrating electrode without being in contact with any one of the circuit elements; a second conductive path electrically connected between the first penetrating electrode and the third penetrating electrode without being in contact with any one of the circuit elements; and a third conductive path electrically connected between the second penetrating electrode and the fourth penetrating electrode without being in contact with any one of the circuit elements. | 05-30-2013 |
20130134507 | SEMICONDUCTOR DEVICE INCLUDING SHARED PILLAR LOWER DIFFUSION LAYER - A semiconductor device includes a high-breakdown voltage transistor in which at least first and second vertical transistor are connected in series to each other. The first vertical transistor includes a first unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The second vertical transistor includes a second unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared. | 05-30-2013 |
20130134548 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, the thickness of an insulating film formed in a through hole is reduced, while an annular groove having an insulating material embedded therein is provided so as to ensure a sufficient total thickness of the insulator, whereby a through silicon via is provided with an insulating ring which is improved in both processability and functionality. | 05-30-2013 |
20130134552 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a pair of electromagnetically coupled inductors. Each of the inductors is comprised of a plurality of through electrodes which extend through a semiconductor substrate, and wires which connect the plurality of through electrodes in series. | 05-30-2013 |
20130134556 | SEMICONDUCTOR DEVICE - This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion. | 05-30-2013 |
20130134584 | SEMICONDUCTOR DEVICE HAVING WIRING PAD AND WIRING FORMED ON THE SAME WIRING LAYER - Disclosed herein is a device that includes a first wiring provided as a first-level wiring layer and elongated in a first direction; and a first wiring pad provided as the first-level wiring layer, the first wiring pad being rectangular and including a first side edge that is elongated in the first direction and a second side edge that is elongated in a second direction crossing to the first direction, the first side edge being greater in length than the second side edge, the first wiring pad being greater in length in the second direction than the first wiring. | 05-30-2013 |
20130134788 | SEMICONDUCTOR DEVICE - A semiconductor device includes an inverter constituted from first and second transistors connected in series between a first power supply and a second power supply and a first circuit connected between the first and second transistors which have gates coupled together. The first circuit includes a first resistance element of a positive temperature characteristic and a third transistor connected to each other in parallel. The third transistor operates at least in a region where a resistance between drain and source terminals exhibits a negative temperature characteristic. | 05-30-2013 |
20130135010 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A device including first and second semiconductor chips, each of first and second semiconductor chips including first to M-th penetration electrodes, M being an integer equal to or greater than 3, each of the first to M-th penetration electrodes penetrating through a semiconductor substrate, and the first semiconductor chip including a first input circuit coupled to the M-th penetration electrode of the first semiconductor chip at an input node thereof, the first and second semiconductor chips being stacked with each other in which the first to M-th penetration electrodes of the second semiconductor chip are vertically arranged respectively with the first to M-th penetration electrodes of the first semiconductor chip, in which the first to (M−2)-th penetration electrodes of the second semiconductor chip are electrically coupled to the second to (M−1)-th penetration electrodes of the first semiconductor chip, respectively. | 05-30-2013 |
20130135039 | INTERNAL POWER SUPPLY CIRCUIT, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units. | 05-30-2013 |
20130135916 | MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND DATA REGISTER BUFFER - Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors. | 05-30-2013 |
20130135950 | SEMICONDUCTOR MEMORY DEVICE AND READ WAIT TIME ADJUSTMENT METHOD THEREOF, MEMORY SYSTEM, AND SEMICONDUCTOR DEVICE - A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals edge specifying information that takes a selected one of first and second states, the edge specifying information being supplied to the device to cause the device to activate a data strobe signal at a first timing when the selected one of the edge specifying information is the first state and at a second timing, that is different from the first timing, when the edge specifying information is the second state, the control circuit being further configured to generate and output onto the set of first terminals a read command, the read command being supplied to the device to cause the device to return to the controller a data signal. | 05-30-2013 |
20130137216 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS STACKED ONE ANOTHER - Disclosed herein is a method of manufacturing a semiconductor device that includes stacking a plurality of semiconductor chips to form a first chip laminated body, providing an underfill material to fill gaps between the semiconductor chips so that a fillet portion is formed around the first chip laminated body, and trimming the fillet portion to form a second chip laminated body. | 05-30-2013 |
20130137217 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, comprising preparing a wiring substrate and mounting a first rectangular semiconductor chip having plural of first electrodes arranged along short sides thereof on the wiring substrate. A second rectangular semiconductor chip having plural of second electrodes arranged along short sides thereof is stacked on the first semiconductor chip so that the short sides of the second semiconductor chip are perpendicular to the short sides of the first semiconductor chip and that gaps are formed between the wiring substrate and short side portions of the second semiconductor chip. The method further comprises filling the gaps with a first resin from locations near long sides of the second semiconductor chip in a direction parallel to the short sides of the second semiconductor chip. The first and the second electrodes are connected to connection pads of the wiring substrate by first and second wires, respectively. | 05-30-2013 |
20130138898 | MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND COMMAND ADDRESS REGISTER BUFFER - Disclosed herein is a memory module that includes a plurality of command address connectors formed on the module substrate, a plurality of memory devices mounted on the module substrate, and a plurality of command address register buffers mounted on the module substrate. The command address connectors receive a command address signal from outside. The memory devices include a plurality of first memory devices and a plurality of second memory devices. The command address register buffers include a first command address register buffer that supplies the command address signal to the first memory devices and a second command address register buffer that supplies the command address signal to the second memory devices. | 05-30-2013 |
20130140067 | WAFER OR CIRCUIT BOARD AND JOINING STRUCTURE OF WAFER OR CIRCUIT BOARD - A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion | 06-06-2013 |
20130140628 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar. | 06-06-2013 |
20130140674 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line. | 06-06-2013 |
20130141994 | SEMICONDUCTOR DEVICE HAVING SKEW DETECTION CIRCUIT MEASURING SKEW BETWEEN CLOCK SIGNAL AND DATA STROBE SIGNAL - Disclosed herein is a semiconductor device that includes a clock terminal supplied with a first clock signal from outside; a dividing circuit dividing a frequency of the first clock signal to generate a plurality of second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal, the multiplexer having a predetermined operating delay time; a data strobe terminal supplied with a first data strobe signal from outside; a strobe signal generation circuit adding the predetermined operating delay time to the first data strobe signal to generate a second data strobe signal; and a skew detection circuit measuring a skew between the third clock signal and the second data strobe signal. | 06-06-2013 |
20130143384 | HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. | 06-06-2013 |
20130147013 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal. | 06-13-2013 |
20130147038 | SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS WITHOUT OCCURRING OF CRACK - A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern. | 06-13-2013 |
20130147042 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias. | 06-13-2013 |
20130148412 | SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE - A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats. | 06-13-2013 |
20130153898 | SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIP STACKED WITH ONE ANOTHER - Disclosed herein is a device that includes: external terminals; a first chip including a first control circuit that generates a first control signal; and a second chip stacked with the first chip. The second chip includes: a first test terminal supplied with a first test signal and being free from connecting to any one of the external terminals; a second test terminal supplied with the first test signal and coupled to one of the external terminals without connecting to any one of control circuits of the first chip; a first normal terminal supplied with the first control signal and coupled to another of the external terminals with an intervention of the first control circuit of the first chip; and a first selection circuit including first input node coupled in common to the first and second test terminals and the second input node coupled to the first normal terminal. | 06-20-2013 |
20130153899 | SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS - Disclosed herein is a device that including a first chip having first to fourth terminals and a second chip having fifth to seventh terminals. The first chip further includes a penetration electrode connected between the first and fourth electrodes and a first internal node coupled to of which an electrical potential being changed in response to an electrical potential of the first terminal. The second chip further includes a second internal node coupled to of which an electrical potential being changed in response to an electrical potential of the fifth terminal. The first internal node is electrically coupled to both the second terminal and the sixth terminal. The second internal node is electrically coupled to both the third terminal and the seventh terminal. | 06-20-2013 |
20130154025 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR STABILIZING VARIATION OF POWER SUPPLY VOLTAGE - Disclosed herein is a semiconductor device that includes a first line supplied with a first voltage, a second line supplied with a second voltage, a first node, at least one first capacitor connected between the first line and the first node, at least one second capacitor connected between the node and the second line, and a protective element connected between the first node and the second line in parallel to the second capacitor. | 06-20-2013 |
20130154056 | SEMICONDUCTOR DEVICE - In a semiconductor device including a capacitor which has an upper electrode, a polycrystalline silicon layer on the upper electrode, and a metallic member on the polycrystalline silicon layer, the polycrystalline silicon layer includes germanium so that an upper portion of the polycrystalline silicon layer is lower than a lower portion thereof in a concentration of germanium. | 06-20-2013 |
20130154057 | Method for Fabricating a DRAM Capacitor - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO | 06-20-2013 |
20130154096 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a manufacturing method of a barrier layer, a via hole is formed in an insulating layer that covers a conductive layer over a substrate, and then the barrier layer is formed in the via hole. The barrier layer is provided by forming a second titanium nitride film after forming a first titanium nitride film. The second titanium nitride film is formed using a method having a weak anisotropy than the first titanium nitride film. | 06-20-2013 |
20130155792 | SEMICONDUCTOR DEVICE HAVING DATA TERMINAL SUPPLIED WITH PLURAL WRITE DATA IN SERIAL - Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals. | 06-20-2013 |
20130155798 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively. | 06-20-2013 |
20130161733 | SEMICONDUCTOR DEVICE - Disclosed herein a semiconductor device, which comprises: a vertical MOS transistor that has an upper diffusion layer, and a first lower diffusion layer disposed at a lower position than the upper diffusion layer; and a first diode that has a first well isolated from the first lower diffusion layer, and a second lower diffusion layer disposed at a lower position than the upper diffusion layer and formed in the first well. A surge voltage is discharged across the second lower diffusion layer and the first well when the surge voltage is applied. | 06-27-2013 |
20130161738 | SEMICONDUCTOR DEVICE - A semiconductor device | 06-27-2013 |
20130161827 | SEMICONDUCTOR CHIP HAVING PLURAL PENETRATION ELECTRODE PENETRATING THERETHROUGH - Disclosed herein is a semiconductor chip that includes: a plurality of penetration electrodes each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and a third penetration electrode; and a wiring configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode. | 06-27-2013 |
20130162275 | SEMICONDUCTOR DEVICE HAVING COMMAND MONITOR CIRCUIT - A semiconductor device includes a plurality of channels, a plurality of command monitor circuits provided corresponding to the plurality of channels, respectively, and a plurality of signal lines coupled in common to the plurality of command monitor circuits. Each of the plurality of command monitor circuits includes a selector configured to receive a plurality of input signals and selectively output a plurality of selected signals among the input signals, based on a first selection information, and an output circuit coupled between the selector and the plurality of signal lines, and configured to output the selected signals to the plurality of signal lines, respectively, based on a second selection information. One of the plurality of command monitor circuits is selected to output the selected signals to the plurality of signal lines while the remaining of the command monitor circuits is non selected, based on the second selection information. | 06-27-2013 |
20130162282 | SEMICONDUCTOR DEVICE HAVING POTENTIAL MONITORING TERMINAL TO MONITOR POTENTIAL OF POWER-SUPPLY LINE - Disclosed herein is a device that includes an internal circuit, a first terminal supplied with a first voltage, a first power-supply line coupled between the first terminal and the internal circuit, a potential monitoring terminal, and a first switch coupled between the internal power-supply line and the potential monitoring terminal. | 06-27-2013 |
20130162302 | SEMICONDUCTOR DEVICE HAVING DATA OUTPUT CIRCUIT IN WHICH SLEW RATE THEREOF IS ADJUSTABLE - Disclosed herein is a device that includes: a first circuit configured to operate on a first power voltage to produce a first set of slew rate control signals; a second circuit configured to operate on a second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and a third circuit configured to operate on the second power voltage to produce a signal at a rate that is controllable in response to the second set of slew rate control signals. | 06-27-2013 |
20130162308 | SEMICONDUCTOR DEVICE THAT CAN ADJUST PROPAGATION TIME OF INTERNAL CLOCK SIGNAL - Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal. | 06-27-2013 |
20130163303 | SEMICONDUCTOR DEVICE HAVING MULTI-LEVEL WIRING STRUCTURE - Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer. | 06-27-2013 |
20130163353 | SEMICONDUCTOR DEVICE HAVING ODT FUNCTION - Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other. | 06-27-2013 |
20130163361 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input. | 06-27-2013 |
20130164909 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an insulating isolation portion in a groove of a substrate, forming a projection portion in which an upper portion of the insulating isolation portion projects from a principal surface of the substrate, forming a sidewall spacer covering a side surface of the projection portion and part of the principal surface of the substrate along the side surface of the projection portion, and forming a first trench in the substrate by etching the substrate using the sidewall spacer as a mask. | 06-27-2013 |
20130173864 | SEMICONDUCTOR DEVICE INCLUDING ROW CACHE REGISTER - Disclosed herein is a device that includes a memory cell array having a plurality of pages, a row cache register, and an array control circuit. The array control circuit is configured to: select one of the pages as a selected page to form an electrical path between the selected page and the row cache register in response to a first command with a row address; cut the electrical path between the selected page and the row cache register; and form the electrical path again between the selected page and the row cache register in response to a second command without the row address. | 07-04-2013 |
20130173973 | DEVICE - A device includes memory banks, each having a plurality of memory cells with respective error data output circuits. Each of the error data output circuits outputs first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank. A test control circuit has first error data synthesis circuits and second to (M+1)-th error data synthesis circuits, each of which synthesizes the first to M-th error data from a corresponding error data output circuit and outputs the synthesized data as first test data. Each of the error data synthesis circuits synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data. | 07-04-2013 |
20130175682 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film. | 07-11-2013 |
20130181271 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face. | 07-18-2013 |
20130181345 | SEMICONDUCTOR DEVICE HAVING PENETRATION ELECTRODE PENETRATING THROUGH SEMICONDUCTOR SUBSTRATE - Disclosed herein is a device that includes: a semiconductor substrate having a first surface on which a plurality of circuit elements are formed and a second surface opposite to the first surface; an insulating layer covering the second surface of the semiconductor substrate; and a penetration electrode having a body section that penetrates through the semiconductor substrate and a protruding section that is connected to one end of the body section and protrudes from the second surface of the semiconductor substrate. The second surface of the semiconductor substrate is covered with the protruding section of the penetration electrode without intervention of the insulating layer. | 07-18-2013 |
20130182516 | SEMICONDUCTOR DEVICE HAVING COUNTER CIRCUIT - A semiconductor device is disclosed which comprises a clock generating circuit generating first and second divided clocks by dividing an input clock by first and second division number, respectively, and a counter circuit including a shift register having a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on setting information. The counter circuit individually controls operation timings of the stages of the shift register by selectively supplying either of the first and second divided clocks to each stage of the shift register, and either of signals from the stages of the shift register is extracted and outputted as the output signal. | 07-18-2013 |
20130187294 | SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 07-25-2013 |
20130193396 | VARIABLE RESISTIVE ELEMENT, AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A variable resistive element that performs a forming action at small current and a stable switching operation at low voltage and small current, and a low-power consumption large-capacity non-volatile semiconductor memory device including the element are realized. The element includes a variable resistor between first and second electrodes. The variable resistor includes at least two layers, which are a resistance change layer and high-oxygen layer, made of metal oxide or metal oxynitride. The high-oxygen layer is inserted between the first electrode having a work function smaller than the second electrode and the resistance change layer. The oxygen concentration of the metal oxide of the high-oxygen layer is adjusted such that the ratio of the oxygen composition ratio to the metal element to stoichiometric composition becomes larger than the ratio of the oxygen composition ratio to the metal element of the metal oxide forming the resistance change layer to stoichiometric composition. | 08-01-2013 |
20130193586 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF WIRING LAYERS AND DESIGNING METHOD THEREOF - A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. Because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. | 08-01-2013 |
20130194035 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V | 08-01-2013 |
20130194857 | SEMICONDUCTOR DEVICE HAVING BIT LINES HIERARCHICALLY STRUCTURED - Disclosed herein is a device that includes: a sense amplifier circuit activated in response to a first control signal; a first global bit line coupled to the sense amplifier circuit; a first local bit line; a first transistor electrically coupled between the first global bit line and the first local bit line, the first transistor being rendered conductive in response to a second control signal; a first memory cell; a first cell transistor electrically coupled between the first local bit line and the first memory cell, the first cell transistor being rendered conductive in response to a third control signal; and a control circuit producing the first, second, and third control signals such that the second control signal is produced after producing the third control signal and the first control signal is produced after producing the second and third control signals. | 08-01-2013 |
20130201774 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM - A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data. | 08-08-2013 |