| Patent application number | Description | Published |
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| 20140015054 | FIELD EFFECT TRANSISTOR DEVICES HAVING THICK GATE DIELECTRIC LAYERS AND THIN GATE DIELECTRIC LAYERS - A semiconductor device includes a substrate, a fin arranged on the substrate, a first field effect transistor (FET) comprising a first gate stack disposed over the a portion of the fin, the first gate stack including a polysilicon layer and a silicide material disposed on the polysilicon layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the first FET, and a second effect transistor (FET) comprising a second gate stack disposed over the a portion of the fin, the second gate stack including a metal gate material layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the second FET. | 01-16-2014 |
| 20140197370 | OVERLAP CAPACITANCE NANOWIRE - A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectric regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire. | 07-17-2014 |
| 20140197371 | OVERLAP CAPACITANCE NANOWIRE - A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectic regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire. | 07-17-2014 |
| 20140339507 | STACKED SEMICONDUCTOR NANOWIRES WITH TUNNEL SPACERS - A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material. A gate structure is formed within the areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material. | 11-20-2014 |
| 20140339611 | STACKED SEMICONDUCTOR NANOWIRES WITH TUNNEL SPACERS - A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material. A gate structure is formed within the areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material. | 11-20-2014 |
| 20140353796 | Fin eFuse Formed by Trench Silicide Process - A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide. | 12-04-2014 |
| 20140370681 | FIELD-EFFECT TRANSISTOR (FET) WITH SOURCE-DRAIN CONTACT OVER GATE SPACER - A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate. | 12-18-2014 |
| 20140374800 | OVERLAPPED III-V FINFET WITH DOPED SEMICONDUCTOR EXTENSIONS - A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin. | 12-25-2014 |
| 20140374878 | MEMORY CELL WITH INTEGRATED III-V DEVICE - A method including forming an oxide layer on a top of a substrate; forming a deep trench capacitor in the substrate; bonding a III-V compound semiconductor to a top surface of the oxide layer; and forming a III-V device in the III-V compound semiconductor. | 12-25-2014 |
| 20140377918 | OVERLAPPED III-V FINFET WITH DOPED SEMICONDUCTOR EXTENSIONS - A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin. | 12-25-2014 |
| 20150048476 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches. | 02-19-2015 |
| 20150061017 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming at least one gate structure over a plurality of fin structures. The method further includes removing dielectric material adjacent to the at least one gate structure using a maskless process, thereby exposing an underlying epitaxial layer formed adjacent to the at least one gate structure. The method further includes depositing metal material on the exposed underlying epitaxial layer to form contact metal in electrical contact with source and drain regions, adjacent to the at least one gate structure. The method further includes forming active areas and device isolation after the formation of the contact metal, including the at least one gate structure. The active areas and the contact metal are self-aligned with each other in a direction parallel to the at least one gate structure. | 03-05-2015 |
| 20150061018 | SPACERLESS FIN DEVICE WITH REDUCED PARASITIC RESISTANCE AND CAPACITANCE AND METHOD TO FABRICATE SAME - A structure includes a substrate having an insulator layer and a plurality of elongated semiconductor fin structures disposed on a surface of the insulator layer. The fin structures are disposed substantially parallel to one another. The structure further includes a plurality of elongated sacrificial gate structures each comprised of silicon nitride. The sacrificial gate structures are disposed substantially parallel to one another and orthogonal to the plurality of fin structures, where a portion of each of a plurality of adjacent fin structures is embedded within one of the sacrificial gate structures leaving other portions exposed between the sacrificial gate structures. The structure further includes a plurality of semiconductor source/drain (S/D) structures disposed over the exposed portions of the fin structures between the sacrificial gate structures. The embodiments eliminate a need to form a conventional spacer on the fin structures. | 03-05-2015 |
| 20150064854 | SPACERLESS FIN DEVICE WITH REDUCED PARASITIC RESISTANCE AND CAPACITANCE AND METHOD TO FABRICATE SAME - A structure includes a substrate having an insulator layer and a plurality of elongated semiconductor fin structures disposed on a surface of the insulator layer. The fin structures are disposed substantially parallel to one another. The structure further includes a plurality of elongated sacrificial gate structures each comprised of silicon nitride. The sacrificial gate structures are disposed substantially parallel to one another and orthogonal to the plurality of fin structures, where a portion of each of a plurality of adjacent fin structures is embedded within one of the sacrificial gate structures leaving other portions exposed between the sacrificial gate structures. The structure further includes a plurality of semiconductor source/drain (S/D) structures disposed over the exposed portions of the fin structures between the sacrificial gate structures. The embodiments eliminate a need to form a conventional spacer on the fin structures. A method to fabricate the structure is also disclosed. | 03-05-2015 |
| 20150064892 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming at least one gate structure over a plurality of fin structures. The method further includes removing dielectric material adjacent to the at least one gate structure using a maskless process, thereby exposing an underlying epitaxial layer formed adjacent to the at least one gate structure. The method further includes depositing metal material on the exposed underlying epitaxial layer to form contact metal in electrical contact with source and drain regions, adjacent to the at least one gate structure. The method further includes forming active areas and device isolation after the formation of the contact metal, including the at least one gate structure. The active areas and the contact metal are self-aligned with each other in a direction parallel to the at least one gate structure. | 03-05-2015 |
| 20150064897 | PROCESS VARIABILITY TOLERANT HARD MASK FOR REPLACEMENT METAL GATE FINFET DEVICES - Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall. | 03-05-2015 |
| 20150069328 | STACKED NANOWIRE DEVICE WITH VARIABLE NUMBER OF NANOWIRE CHANNELS - A method of forming a semiconductor structure including forming a stack of layers on a top surface of a substrate, the stack of layers including alternating layers of a semiconductor material and a sacrificial material, where a bottommost layer of the stack of layers is a top semiconductor layer of the substrate, patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels including the semiconductor material, and the plurality of sacrificial spacers including the sacrificial material, and removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack. | 03-12-2015 |
