Patent application number | Description | Published |
20080201618 | Method for Running a Computer Program on a Computer System - Errors which may be detected by an error detection unit may occur during execution of a computer program which runs on a computer system and includes at least one run-time object. In order to handle a detected error particularly flexibly and to keep the computer system available as much as possible, an error handling routine is selected from a pre-selectable set of error handling routines as a function of an identifier assigned to the run-time object and the selected error handling routine is executed. | 08-21-2008 |
20080209170 | Method and Device for Performing Switchover Operations and for Signal Comparison in a Computer System Having at Least Two Processing Units - A method for switchover and for signal comparison is used in a computer system having at least two processing units, a switchover device being provided, and a switch taking place between at least two operating modes, and a comparison device being provided; and a first operating mode corresponds to a compare mode, and a second operating mode corresponds to a performance mode, wherein at least two analog signals of the processing units are compared in that at least one analog signal is converted into at least one digital value. | 08-28-2008 |
20080263340 | Method and Device for Analyzing a Signal from a Computer System Having at Least Two Execution Units - A method and device for analyzing a signal from a computer system having at least two execution units, in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, characterized in that, in the computer system, a mode signal and/or changes in the mode signal, which are indicative of the current operating mode, are generated, and at least the changes in the mode signal and/or this mode signal itself are made available outside of the computer system for analysis purposes. | 10-23-2008 |
20080270660 | Method and Device for Switching Over in a Computer System Having at Least Two Execution Units - A device and method for switching over in a computer system having at least two execution units are provided, in which switchover units are included which are designed in such a way that they switch between at least two operating modes, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. A programmable interrupt controller is assigned to each execution unit, and a storage element is included, in which information is stored that describes at least parts of a configuration of at least one of these interrupt controllers. | 10-30-2008 |
20080270746 | Method and Device for Performing Switchover Operations and for Comparing Signals in a Computer System Having at Least Two Processing Units - A method and a device for performing switchover operations and for comparing signals in a computer system having at least two processing units, a switchover device being provided, and switchover operations being carried out between at least two operating modes, a comparator being provided, and a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode. At least two analog signals of the processing units are compared in such a way that, as a function of these signals, a difference is formed. | 10-30-2008 |
20080270747 | Method and Device for Switching Over Between Operating Modes of a Multi-Processor System Using at Least One External Signal - A method for a switchover in a computer system having at least two execution units, a switchover being performed between at least two operating modes, and a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode, wherein the switchover is triggered by at least one signal, which is generated outside the computer system. | 10-30-2008 |
20080270830 | Data Processing System and Method for Operating a Data Processing System - To improve the availability of a data processing system despite possible memory errors, when reading a data word from a memory cell, the integrity of the data word is checked on the basis of redundant additional information, and if the data word turns out to be corrupted, an error correction procedure is performed in which the reliability performance of the memory cell is checked and, if the memory cell is found to be operational, its contents are restored. | 10-30-2008 |
20080288758 | Method and Device for Switching Over in a Computer System Having at Least Two Execution Units - A method and device for switching over in a computer system having at least two execution units, switching being carried out between at least two operating modes, and the operating modes corresponding to states of the computer system, a first state corresponding to a comparison mode and a second state corresponding to a performance mode, so that events may occur by which the computer system can attain an otherwise undefined state, in which, in response to the occurrence of any such event, the second state is assumed, which corresponds to a performance mode. | 11-20-2008 |
20080313384 | Method and Device for Separating the Processing of Program Code in a Computer System Having at Least Two Execution Units - A method and a device are provided for separating the processing of program code in a computer system having at least two execution units, in which method and device switching over takes place between at least two operating modes, and a first operating mode corresponds to a comparison mode and a second operating mode corresponds to a performance mode, and the at least two execution units process the same program code in the comparison mode. When there is a switchover from the comparison mode to the performance mode, a separation in the program code takes place in that each execution unit has an identifier assigned to it, and, as a function of the identifier, different program code is assigned to at least two execution units. | 12-18-2008 |
20080320287 | Method and Device for Performing Switchover Operations in a Computer System Having at Least Two Processing Units - A method and device for performing switchover operations in a computer system having at least two processing units, a switchover device, and a comparison device, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, information being compared in the comparison mode. In the case of asynchronous operation of the at least two processing units in the comparison mode, a synchronization signal is applied to one interrupt input of at least one of the processing units. | 12-25-2008 |
20080320340 | Method and Device for Performing Switchover Operations and for Comparing Data in a Computer System Having at Least Three Execution Units - A method and a device for performing switchover operations and for comparing data in a computer system having at least three processing units are provided, in which switchover unit is provided, a switchover operations being carried out between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode are provided. Provision is made in the comparison mode for a voting, at least as a two-out-of-three weighting, and a control unit is provided which may be used to set the voting. | 12-25-2008 |
20090037705 | Method and Device for Processing Data Words and/or Instructions - A method for processing data words and/or instructions, a distinction being made, in the processing, between at least two operating modes, and a first operating mode corresponding to a compare mode and a second operating mode corresponding to a performance mode, in the compare mode, a comparator unit being activated and this comparator unit being deactivated in the performance mode, wherein the comparator unit is activated for the compare mode as a function of two equal data words and/or instructions getting to be processed and the at least equal data words and/or instructions in each case being distributed by a control unit to the at least two execution units. | 02-05-2009 |
20090044044 | DEVICE AND METHOD FOR CORRECTING ERRORS IN A SYSTEM HAVING AT LEAST TWO EXECUTION UNITS HAVING REGISTERS - A device for correcting errors in a system having at least two execution units having registers is presented, the registers being designed for recording data. The device has comparison device(s) that are set up such that through a comparison of data that are provided for storage in the registers, a deviation and thus an error may be ascertained. Furthermore, at least one shadow register that is set up such that data concerning the data of the registers may be stored therein, and device(s) are provided for restoring error-free data in at least one register on the basis of the data in the at least one shadow register when an error is detected. This device may be used to improve the safety of a multicore processor. | 02-12-2009 |
20090044048 | Method and device for generating a signal in a computer system having a plurality of components - A method and device for generating a signal in a computer system having a plurality of components, at least two execution units being provided as two components, and a switchover means being provided as an additional component, in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, wherein, in one component of the computer system, a mode signal, indicative of the current operating mode, and/or changes in a mode signal are generated, and at least the changes in the mode signal and/or the mode signal itself are made available outside of the component. | 02-12-2009 |
20090055674 | Method and device for a switchover and for a data comparison in a computer system having at least two processing units - A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data. | 02-26-2009 |
20090119540 | Device and method for performing switchover operations in a computer system having at least two execution units - A device and method for performing switchover operations in a computer system having at least two execution units, a changeover switch being provided which switches between at least two operating modes, a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode, in addition, a comparator being provided which is activated in the comparison mode, in which an arrangement provides desired switchover detection, the arrangement for desired switchover detection controlling the changeover switch in order to switch from one operating mode to another. | 05-07-2009 |
20090177890 | Method and Device for Forming a Signature - A device and a method are for forming a signature for use in a transmitter unit or a receiver unit of a communication system. To speed up the formation of a signature and thus the data transfer between a computer unit (e.g., a microcontroller) and a communication controller of the transmitter unit or the receiver unit, the device is arranged as hardware and the device forms the signature for data which are to be transferred from a computer unit of the transmitter unit to a communication controller of the transmitter unit for the purpose of data transmission via a communication medium of the communication system or which are to be transferred from a communication controller of the receiver unit to a computer unit of the receiver unit for further processing. | 07-09-2009 |
20090210777 | Method and Device for Comparing Data in a Computer System Having at Least Two Execution Units - A method for comparing data in a computer system having at least two execution units, the comparison of the data taking place in a comparison unit and each execution unit processing input data and generating output data, wherein one execution unit specifies to the comparison unit that the next piece of output data is to be compared to a piece of output data of the at least second execution unit, and thereupon a comparison of the at least two output data takes place. | 08-20-2009 |
20090217107 | Method and Device for Data Processing - A method and device for data processing having at least three identical or similar execution units, wherein at least one comparator exists and at least two execution units are grouped such that the output signals of the at least two execution units are connected with the at least one comparator and compared. | 08-27-2009 |
20090217279 | Method and Device for Controlling a Computer System - A method and device for controlling a computer system having at least two execution units, a switchover taking place between at least two operating modes, and a first operating mode corresponds to a compare mode, and a second operating mode corresponds to a performance mode, wherein at least one set of run-time objects is defined, and a control program is provided, in particular a scheduler, which assigns resources of the computer system to the run-time objects as a function of an item of information regarding the operating mode. | 08-27-2009 |
20100005244 | Device and Method for Storing Data and/or Instructions in a Computer System Having At Least Two Processing Units and At Least One First Memory or Memory Area for Data and/or Instructions - A device and method for storing data and/or instructions in a computer system having at least two processing units and at least one first memory or memory area for data and/or instructions, wherein a second memory or memory area is included in the device, the device being designed as a cache memory system and equipped with at least two separate ports, and the at least two processing units accessing via these ports the same or different memory cells of the second memory or memory area, the data and/or instructions from the first memory system being stored temporarily in blocks. | 01-07-2010 |
20100011183 | METHOD AND DEVICE FOR ESTABLISHING AN INITIAL STATE FOR A COMPUTER SYSTEM HAVING AT LEAST TWO EXECUTION UNITS BY MARKING REGISTERS - A method for establishing an initial state in a computer system having at least two execution units, a switchover between a performance mode and a compare mode being performed, and during the switchover from the performance mode to the compare mode, an initial state for the compare mode being generated, wherein memories or memory areas that are potentially to be adapted for the initial state are provided with an identifier that indicates whether or not the data and/or instructions in these memories or memory areas must be modified for the initial state. | 01-14-2010 |
20100013683 | METHOD FOR ERROR HANDLING - In a method for error handling in transmission of a datum over a communications system, at least two data words consisting of bits are generated for the datum in accordance with a predefined coding rule, and one of the generated data words is selected taking into consideration a running digital sum formed over the corresponding data word, and the running digital sum of the selected data word is used for the formation of a first running digital sum. The selected data word is converted into a code data word, and a bit of the data word is in each case assigned a two-bit string with two different single-bit values. The code data word and the first running digital sum are transmitted. The received code data word is examined to ascertain whether an erroneous two-bit string exists, in which case the error is corrected using the first running digital sum. | 01-21-2010 |
20100046594 | Method and device for decoding a signal - In a method and a device for decoding a signal, the signal is transmitted via at least one connecting line of a data transmission system, in a user of the data transmission system receiving the signal. It is provided to measure the interval of a change—provided compulsorily in a transmission protocol used in the data transmission system—of the signal from rising to falling or from falling to rising edge. A tendency for an asymmetrical delay of the signal can be ascertained from the measured interval. The sampling of the bits of the received signal can be improved as a function of the interval or of the asymmetrical delay, for example, by setting the sampling instant in variable fashion. Alternatively, the interval or the asymmetrical delay can be utilized for diagnostic purposes. | 02-25-2010 |
20100192021 | Method and Device for Monitoring Functions of a Computer System - The invention relates to a method and device for monitoring operations of a computer system comprising at least two execution units, wherein switching means are provided and make it is possible to switch at least two operating modes to each other and comparison means are provided, the first operating mode corresponds to the comparison mode and the second operating mode corresponds to the performance mode and the first operation is monitored by the second operation, in the comparison mode said second operation is run on at least two execution units and each second operation which is run on at least two execution units monitors the first operation. | 07-29-2010 |
20100199046 | METHOD AND DEVICE FOR CONTROLLING A MEMORY ACCESS IN A COMPUTER SYSTEM HAVING AT LEAST TWO EXECUTION UNITS - A method and device for controlling memory access in a computer system having at least two execution units, a buffer area, in particular a cache memory area being provided for each execution unit, and furthermore a switchover device and a comparison device being provided, the system switching between a performance mode and a compare mode, wherein in the performance mode each execution unit accesses the buffer area assigned to it and in the compare mode both execution units access one buffer area that can be predefined, the buffer areas being configurable. | 08-05-2010 |
20100208886 | METHOD AND DEVICE FOR MANIPULATION-PROOF TRANSMISSION OF DATA - A method for the manipulation-proof transmission of data from a transmitter to a receiver, a test part being generated in the transmitter from the data using a secret key and communicated together with the data to the receiver, where a verification test part is generated from the received data using the same secret key and is compared to the received test part. Before the generation of the test part, the data are nonlinearly compressed using at least one feedback shift register. In addition, a device for the manipulation-proof transmission of data. | 08-19-2010 |
20100211819 | METHOD AND A DEVICE FOR CONTROLLING A MEMORY ACCESS IN A COMPUTER SYSTEM HAVING AT LEAST TWO EXECUTION UNITS - A method and device for controlling memory access in a computer system having at least two execution units, a buffer, in particular a cache being provided for each execution unit, and furthermore a switchover device and a comparison device being provided, the system switching between a performance mode and a compare mode, wherein in the performance mode each execution unit accesses the buffer assigned to it and in the compare mode both execution units access one buffer. | 08-19-2010 |
20100268923 | METHOD AND DEVICE FOR CONTROLLING A COMPUTER SYSTEM HAVING AT LEAST TWO GROUPS OF INTERNAL STATES - A method and device for controlling a computer system having at least two execution units and having at least two groups of internal states, in particular processor states, in at least one of the execution units, and having a switchover device, through which it is possible to switch between at least two different operating modes, in particular a performance mode and a compare mode, of the computer system, wherein a switchover is triggered by the fact that at least one execution unit changes its internal state. | 10-21-2010 |
20100295571 | Device and Method for Configuring a Semiconductor Circuit - A device and method for configuring a semiconductor circuit having at least two identical or similar functional units, the faulty unit being identified and deactivated if an error occurs in at least one of the identical or similar functional units. | 11-25-2010 |
20110022281 | VEHICLE-SUPPORTED DATA PROCESSING SYSTEM - A vehicle-supported data processing system includes a plurality of processing units communicating with one another via a bus system, which are each supplied with operating power by at least one of the at least two different vehicle electrical systems. Multiple transmitter units for control information and multiple receiver units for the control information are among the processing units. The bus system is a ring bus, in which each processing unit is connected to at least two adjacent processing units by a bus segment in each case. The ring bus is divided, by potential separating devices, which are incorporated in the bus segments which connect processing units powered by different vehicle electrical systems, into a number of sections, which is smaller than the number of the processing units. | 01-27-2011 |
20110029284 | SIGNAL ACQUISITION DEVICE - A signal acquisition device which receives an input signal, a physical data and a timing data to generate an output data. The signal acquisition device keeps monitoring the input signal for a valid edge. When a valid edge is detected, the signal acquisition device reads the physical data from a physical data processing module and a timing data from a timing module to generate the output data which comprises the new state of the input signal, the physical data and the timing data. The output data is written to a storage arrangement and also sent out to CPU or any other devices. | 02-03-2011 |
20110125997 | METHOD AND DEVICE FOR CONTROLLING A COMPUTER SYSTEM - A method and a device for controlling a computer system having at least two execution units, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. At least one set of runtime objects is defined; at least one identifier is assigned to each runtime object of the defined set; and the identifier assigns at least the two operating modes to the runtime object. | 05-26-2011 |
20110302426 | Method for generating a bit vector - A method and a circuit configuration for generating a bit vector are described. At least two configurations, each having state machines of the same design, are used, to whose inputs an input signal is sent and which generate an output signal as a function of their state, each state machine always having a different state than the other state machine of one configuration, so that the bit vector is generated by a linear gating of the output signals of the state machines of different configurations. | 12-08-2011 |
20120030395 | CIRCUIT CONFIGURATIONS AND METHOD FOR CONTROLLING A DATA EXCHANGE IN A CIRCUIT CONFIGURATION - In a method for controlling a data exchange between at least one set of data sinks and at least one set of data sources in circuit configurations and circuit sequences, which circuit configurations have at least one arbitration unit, the arbitration unit selects a first data sink (data sink arbitration) and a first data source (data source arbitration) according to a predefined sequence, and outputs an address of a first data source and a request signal and an address of a first data sink and a validity signal. Data of the first data source are stored in the first data sink. | 02-02-2012 |
20120121081 | NONLINEAR FEEDBACK SHIFT REGISTER AND METHOD FOR NONLINEAR SIGNATURE FORMATION - A nonlinear feedback shift register for creating a signature for cryptographic applications includes a sequence of series-connected flip-flops which are connected to each other for forming at least one polynomial, with the aid of at least one signal feedback having at least one operator. The flip-flops are connected to at least one switching operator for forming at least two different polynomials, the switching operator switching between the polynomials as a function of an input signal. A method for nonlinear signature formation is also provided. | 05-17-2012 |
20120173878 | DEVICE AND METHOD FOR FORMING A SIGNATURE - A device is described for forming a signature from an input signal (input). According to the present invention, a plurality of transformation elements is provided, each having a finite-state machine, to which, on the input end, in each case the input signal (input) and/or a signal (input′), that is a function of the input signal, is able to be fed, all the finite-state machines are similar and are configured in such a way, particularly able to be initialized, that each finite-state machine always respectively has a different state than do all the other finite-state machines, and the signature is formable as a function of state data of at least one finite-state machine. | 07-05-2012 |
20130054666 | METHOD FOR PREDICTING THE DURATION OF A FUTURE TIME INTERVAL - A method for predicting a value for a length of a future time interval in which a physical variable changes is described, in which at least one measured value for the length of a past time interval and an instantaneously measured value for a length of an instantaneous time interval are taken into account, m values for lengths of past time intervals being added. A first value precedes the instantaneously measured value by k−1, and an mth value precedes the instantaneously measured value by k−m. The m added values are divided by a value for a length of a past time interval which precedes the instantaneously measured value by k. A ratio of the mentioned values is formed. For determining the value to be predicted, an average error is initially added to the instantaneously measured value, forming a sum. The formed ratio is subsequently applied to this sum. | 02-28-2013 |
20130073256 | TIMER MODULE AND METHOD FOR TESTING OUTPUT SIGNALS OF A TIMER MODULE - In a timer module having at least two output channels, the at least two output channels are configurable in such a way that they generate redundant output signals, and the generation of the redundant output signals begins synchronously. In addition, the timer module has provides a comparison of the redundant output signals by an EXOR logic operation and stores a result of the EXOR logic operation in a way that allows the result to be retained for an erroneous comparison until it is reset by an access. | 03-21-2013 |
20130073891 | METHOD FOR CHECKING SIGNAL AND MODULE ACTIVITIES IN A TIMER MODULE AND TIMER MODULE - A timer module having a status register is connectable to an external arithmetic unit and generates at least one activity signal for an internal signal of the timer module and/or an internal unit of the timer module and/or a process within the internal unit, and enters an activity status into a status register in the event of a determined activity, and allows the activity status to be polled and reset by the external arithmetic unit at times determined by the external arithmetic unit. Furthermore, the activity status entered into the status register remains until it is reset by the, external arithmetic unit. | 03-21-2013 |
20130076397 | METHOD AND CIRCUIT CONFIGURATION FOR DETERMINING POSITION MINUS TIME - A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out. | 03-28-2013 |
20130077733 | Circuit Configuration And Method For Distributing Pulses Within A Time Interval - A circuit configuration for generating pulses within a time interval on the basis of an input signal includes a counting unit, a comparator unit and a first adder circuit; the time interval being predicted on the basis of at least two defined changes in input signals; the circuit configuration being configured for triggering at the beginning of the time interval by the first adder circuit on the basis of clock pulses, for generating and outputting pulses; for counting a number of generated and output pulses using the counting unit; | 03-28-2013 |
20130079897 | TIMER MODULE AND METHOD FOR CHECKING AN OUTPUT SIGNAL - A method for checking an output signal of a timer module is provided, the timer module having at least one output module, at least one input module, and at least one logic module. The output signal to be checked is read in into the timer module via an input module in addition to its output via an output module, and in the input module, signal characteristics to be checked are determined for the output signal to be checked. Furthermore, the signal characteristics to be checked are read by the logic module from the input module and the signal characteristics to be checked are compared in the logic module to the predefined values for the signal characteristics. | 03-28-2013 |
20130080104 | METHOD FOR SYSTEMATICALLY TREATING ERRORS - A method for systematically handling errors, and an assemblage for carrying out the method, are presented. The method serves for systematically handing errors for a goniometer in the context of the transfer of position data with a position transducer, the position transducer possessing markings that are sensed with at least one sensor; a profile being deposited in a memory region in connection with said markings; the position transducer generating as a function of its position, by way of the markings, position signals that carry, as data, parameters that are deposited into a further memory region beginning with an address pointer value of 0; said address pointer being incremented with each position signal; and a synchronization between the position signals and the profile being created, and the values stored in the profile being used to modify the number of pulses outputted to the goniometer. | 03-28-2013 |
20130081041 | Circuit arrangement for execution planning in a data processing system - A circuit arrangement and method for a data processing system for executing a plurality of tasks with a central processing unit having a processing capacity allocated to the processing unit; the circuit arrangement being configured to allocate the processing unit to the specific tasks in a time-staggered manner for processing, so that the tasks are processed in an order to be selected and tasks not having a current processing request are skipped over in the order during the processing; the circuit arrangement including a prioritization order control unit to determine the order in which the tasks are executed; and in response to each selection of a task for processing, the order of the tasks being redetermined and the selection being controlled so that for a number N of tasks, a maximum of N time units elapse until an active task is once more allocated processing capacity by the processing unit. | 03-28-2013 |
20130082693 | Device and method for processing signals which represent an angular position of a motor shaft - In an apparatus and a method for processing signals that represent an angular position of a shaft of a motor, a storage unit for storing arrival times of the signals in a memory is provided, the storage unit additionally evaluating a rotation direction datum of the shaft. Storage of the times in the memory is performed in a first sequence in the event of a rotation of the shaft in a first direction, and storage in the memory is performed in a second sequence that is opposite to the first sequence in the event of a rotation of the shaft in a second direction that is opposite to the first direction. | 04-04-2013 |
20130096872 | CIRCUIT ARRANGEMENT AND METHOD FOR EVALUATING SIGNALS OF A CRANKSHAFT SENSOR AND OF A CAMSHAFT SENSOR OF AN INTERNAL COMBUSTION ENGINE - A circuit assemblage and a method for evaluating signals of a crankshaft sensor and of a camshaft sensor of an internal combustion engine are provided, the times at which the signals occur being evaluated. A position signal of a shaft of the internal combustion engine is formed from the times. Storage units are provided which simultaneously store the occurrence times of the signals of the crankshaft sensor and the occurrence times of signals of the camshaft sensor. A decision unit is provided as to whether the position signal is formed from the occurrence times of the signals of the crankshaft sensor or from the occurrence times of the signals of the camshaft sensor. | 04-18-2013 |
20130104141 | DIVIDED CENTRAL DATA PROCESSING, - A circuit configuration for a data processing system and a corresponding method for executing multiple tasks by way of a central processing unit having a processing capacity assigned to the processing unit, the circuit configuration being configured to distribute the processing capacity of the processing unit uniformly among the respective tasks, and to process the respective tasks in time-offset fashion until they are respectively executed. | 04-25-2013 |
20130111189 | Circuit Arrangement for a Data Processing System and Method for Data Processing | 05-02-2013 |
20130204580 | Hardware Data Processing Unit and Method for Monitoring a Cycle Duration of a Routing Unit - A hardware data processing unit has at least one base transmitter module, at least one logic unit, and at least one routing unit. The base transmitter module provides base values of a physical variable. The routing unit arbitrates a group of data nodes associated therewith in a determined sequence. The duration of a cycle is defined by a complete iteration of the determined sequence. The hardware data processing unit has a mechanism that checks the cycle duration. The mechanism carries out a first blocked access to a determined data node of the group to capture and store a first base value from the base transmitter module. The mechanism carries out a second blocked access to the determined data node to capture and store a second base value. The mechanism determines a difference between the first and the second base values. | 08-08-2013 |
20130227331 | Modular Structure for Processing Data - A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method. | 08-29-2013 |
20130346458 | METHOD FOR MONITORING THE OUTPUT OF A RANDOM GENERATOR - An assemblage for monitoring an output of a random generator is provided, which assemblage compares chronologically successive sample values at a sampling point with one another in order to detect a relationship of the compared sample values with one another. | 12-26-2013 |
20130346459 | METHOD FOR GENERATING RANDOM NUMBERS - A method and an assemblage for generating random numbers. In the method, at a ring oscillator that comprises an odd number of inverting elements, values are picked off at at least two sampling points, an odd number of inverting elements being present in each case between at least two directly successive sampling points. | 12-26-2013 |
20140219444 | Method for Generating a Random Output Bit Sequence - A method and a random bit generator for generating a random output bit sequence. In this method, a configuration of 2 | 08-07-2014 |
20140223568 | METHOD FOR SECURELY CHECKING A CODE - A method and a circuit system are provided for securely checking a first code word. The method uses at least one code checker, and provides that the first code word to be checked is transferred into a second code word prior to entry into the code checker. | 08-07-2014 |
20140266473 | METHOD FOR DETECTING A CORRELATION - A method is described for detecting a correlation between at least two ring oscillators and to a system for carrying out the method. In the method a memory field is used in which combinations of concatenations are each assigned a bit. | 09-18-2014 |
20140280413 | METHOD FOR DETECTING A CORRELATION - A method for detecting a correlation of a first ring oscillator with a second ring oscillator and a system for carrying out the method are provided. In the method, combinations of concatenations are compared to chronologically preceding concatenations. | 09-18-2014 |
20140286487 | METHOD FOR GENERATING A ONE-WAY FUNCTION - A method for generating a one-way function, as well as a circuit arrangement, which implements the one-way function, are set forth. | 09-25-2014 |
20140289295 | METHOD FOR GENERATING A RANDOM OUTPUT BIT SEQUENCE - A method and a device for generating a random output bit sequence are put forth. In the case of these, an input is inputted into a set-up of finite state machines. The set-up ascertains an output on the basis of the input; the input being inputted into the set-up, linked to a one-way function. | 09-25-2014 |
20150019602 | METHOD FOR POST-PROCESSING AN OUTPUT OF A RANDOM SOURCE OF A RANDOM GENERATOR - A method and as assemblage for post-processing an output of a random source of a random generator are presented. In the method, an output signal of the random source is compressed, thereby yielding a sequence of compressed signal values that are checked in terms of their distribution. | 01-15-2015 |
20150019603 | Method for checking an output of a random number generator - In a method for checking an output of a random number generator which includes at least one random source, the frequency of occurrence of at least one bit assignment is counted and established in a correlation with the total number of values which are taken into account. | 01-15-2015 |
20150019605 | Method for assessing an output of a random number generator - A method for assessing an output of a random number generator which is provided by two phase-locked loops of the random number generator includes: receiving, by a checking system, the output of the random number generator for at least two sampling cycle, wherein for each sampling cycle (i) the output of the random generator includes a sequence of sample values between a starting value and an end value, and (ii) all sample values between the starting value and the end value in the respective cycle are entered into a signature; and comparing, by the checking system, the signatures from the at least two sampling cycles to one another. | 01-15-2015 |
20150019606 | Method for evaluating an output of a random generator - A method and an assemblage for checking an output of a random generator are presented. In the method, signatures that are respectively created from a sequence of sampled values are compared with one another. | 01-15-2015 |