Patent application number | Description | Published |
20090196282 | METHODS AND APPARATUS FOR PROVIDING QUALITY-OF-SERVICE GUARANTEES IN COMPUTER NETWORKS - An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters. | 08-06-2009 |
20100138372 | COGNITIVE PATTERN MATCHING SYSTEM WITH BUILT-IN CONFIDENCE MEASURE - Artificial neural systems are very powerful tools for pattern matching, classification, feature extraction and signal analysis. Systems to date lack an essential feature of their biological counterparts, a measure of confidence that the network response has actually been trained and is not an artifact. In the proposed artificial neural system one output is a produced (trained) measure of confidence in the remaining outputs i.e. a measure of certainty that the inputs match the training data. | 06-03-2010 |
20110289034 | Neural Processing Unit - The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described. | 11-24-2011 |
20130073679 | METHODS AND APPARATUS FOR PROVIDING QUALITY OF SERVICE GUARANTEES IN COMPUTER NETWORKS - An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters. | 03-21-2013 |
20140032457 | NEURAL PROCESSING ENGINE AND ARCHITECTURE USING THE SAME - A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units. | 01-30-2014 |
20140156907 | SMART MEMORY - Systems and methods to process packets of information using an on-chip processing system include a memory bank, an interconnect module, a controller, and one or more processing engines. The packets of information include a packet header and a packet payload. The packet header includes one or more operator codes. The transfer of individual packets is guided to a processing engine through the interconnect module and through the controller by operator codes included in the packets. | 06-05-2014 |
20140172763 | Neural Processing Unit - The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described. | 06-19-2014 |
20140204943 | SYSTEMS AND METHODS FOR PACKET ROUTING - Systems and methods to route packets of information within an integrated circuit, across one or more boards, racks, blades, and/or chassis, and/or across a connected network of packet processing engines include various modes of operation. Packets are routed to their destination, for example an individual packet processing engine. The packets of information include address-mode indicators, one or more destination port indicators, and/or (long-distance) addresses. | 07-24-2014 |