Patent application number | Description | Published |
20080252349 | DUTY CYCLE CORRECTING CIRCUIT - A duty cycle correcting circuit includes a duty ratio control signal generating block that detects a duty ratio of input clock signals and generates a duty ratio control signal comprising a plurality of bits, a power supply block that supplies a voltage to output nodes, and a signal processing block that controls voltage levels of the output nodes to correspond to voltage levels of the input clock signals in response to the plurality of bits of duty ratio control signals. | 10-16-2008 |
20080252350 | CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE - A circuit for correcting a duty cycle includes a duty ratio digital conversion block configured to output duty ratio information of an input clock signal as plural-bit digital signals, a duty ratio information analyzing block configured to analyze the duty ratio information of the input clock signal, generate edge control signals, and select any one of a plurality of delayed clock signals, and a duty ratio control block configured to control duty ratios of a selected delayed clock signal and the input clock signal in response to the edge control signals. | 10-16-2008 |
20090002039 | POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT - A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal. | 01-01-2009 |
20090003101 | APPARATUS AND METHOD OF SETTING TEST MODE IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal. | 01-01-2009 |
20090058483 | DUTY CYCLE CORRECTING CIRCUIT AND METHOD - A duty cycle correcting circuit includes a duty detector that detects a duty ratio of an output clock signal to output a duty detection signal, a variable delay unit that outputs a delay clock signal obtained by variably delaying a input signal according to the duty detection signal, and a pulse width modulating unit that generates a first clock signal that is at a high level when both the input clock signal and the delay clock signal are at a high level and generates a second clock signal that is at a high level when any of the input clock signal and the delay clock signal is at a high level, wherein the pulse width modulating unit selectively outputs the first clock signal or the second clock signal as the output clock signal. | 03-05-2009 |
20090121784 | POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME - A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal. | 05-14-2009 |
20090146707 | DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes an initial operation setting unit configured to generate an initial operation signal in response to a reference clock signal and an operation start signal; a shift register configured to generate a delay control code in response to the initial operation signal, a phase comparison signal, and an initial setting code; a delay line configured to delay the reference clock signal or a feedback clock signal in response to the initial operation signal and the delay control code, thereby generating a plurality of unit delay clock signals; and an initial delay monitoring unit configured to generate the initial setting code in response to the reference clock signal and the plurality of unit delay clock signals. | 06-11-2009 |
20090206884 | LOCKING STATE DETECTOR AND DLL CIRCUIT HAVING THE SAME - A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal. | 08-20-2009 |
20090273382 | CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE - A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal. | 11-05-2009 |
20100134155 | POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME - A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal. | 06-03-2010 |
20100213920 | POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT - A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal. | 08-26-2010 |
20110012654 | LOCKING STATE DETECTOR AND DLL CIRCUIT HAVING THE SAME - A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal. | 01-20-2011 |
20120194231 | POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT - A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal. | 08-02-2012 |