Patent application number | Description | Published |
20120045214 | METHOD AND APPARATUS FOR BURST MODE CLOCK AND DATA RECOVERY - Provided is an optical line terminator (OLT) to recover packet data and a clock from an optical signal including a silent interval. The OLT may receive packet data and a clock from at least one optical network unit (ONU). Even in a silent interval in which the at least one ONU does not transmit packet data, the OLT may successfully recover the clock. | 02-23-2012 |
20120163799 | Method for Transmitting OAM Message and Processing Error in PON System - A method of transmitting an Operations, Administration and Maintenance (OAM) message and of processing an error in a Passive Optical Network (PON) system is provided. Using an OAM packet format that may be used in common in the PON system, a process of transmitting or receiving an OAM message may be simplified, an efficiency of the process may be increased, and an Optical Network Unit (ONU) may be managed at a high speed. | 06-28-2012 |
20130156426 | LOW POWER OPTICAL NETWORK TERMINAL AND METHOD OF OPERATING LOW POWER OPTICAL NETWORK TERMINAL - Disclosed is a low power optical network terminal (ONT) and a method of operating the low power ONT. The low power ONT may include a network media access control (MAC) processing unit to transmit and receive traffic to and from an optical line terminal (OLT), a switching unit to receive the traffic transmitted from the network MAC processing unit and transmit the traffic to a subscriber terminal and to receive the traffic from the subscriber terminal and transmit the traffic to the OLT, and a control unit to control traffic transmission from the network MAC processing unit when a power mode is a low power mode. | 06-20-2013 |
20130188947 | APPARATUS AND METHOD FOR MONITORING OPTICAL LINE - An apparatus and method for monitoring an optical line is provided. The optical line monitoring apparatus may include a comparison unit to extract first identification information about an optical network terminal (ONT) from reflected data that is reflected and received from the optical line, and to compare the extracted first identification information to predetermined second identification information about the ONT, and a processor to analyze a state of the optical line using the reflected data when the first identification information is identical to the second identification information. | 07-25-2013 |
20130188953 | OPTICAL NETWORK SYSTEM AND METHOD FOR CONTROLLING OPTICAL NETWORK SYSTEM - An optical network system for controlling a passive optical network (PON) in which at least one symmetric optical subscriber terminal and at least one asymmetric optical subscriber terminal coexist is provided. | 07-25-2013 |
20150104174 | METHOD OF CONTROLLING OPTICAL NETWORK UNIT (ONU) IN SLEEP MODE - Provided is a method of saving power in a passive optical network (PON) system including an optical line terminal (OLT) and a plurality of optical network units (ONUs), the OLT including an optical transceiver to communicate with at least one ONU through an optical line, and a controller to control the optical transceiver to transmit an upstream bandwidth map to the ONU at a predetermined transmission interval, wherein the transmission interval is determined based on a desired upstream data service delay time. | 04-16-2015 |
20150229389 | APPARATUS AND METHOD FOR DETECTING OPTICAL LINE FAULT IN PASSIVE OPTICAL NETWORK - Disclosed herein is an apparatus and method for detecting an optical line fault in a Passive Optical Network (PON). The apparatus includes an optical distribution unit configured to, when a multiplexed signal of a downstream light signal and a monitoring light signal is input, distribute the multiplexed signal to an Optical Network Unit (ONU) of a first optical path and to a second optical path. An optical layer management unit is installed in the second optical path and is configured to set a time at which the monitoring light signal of the multiplexed signal provided to the second optical path is received to a starting time of monitoring light measurement, compare a monitoring light signal reflected and returned from the ONU with a signal pattern obtained when no fault occurs, and then determine whether a fault has occurred in a distribution network. | 08-13-2015 |
Patent application number | Description | Published |
20090019349 | METHOD AND SYSTEM FOR EXPOSING GAMES - A game exposing method and system is provided. The game exposing method includes displaying a game web site in a first folder of a file manager application of a user terminal; and displaying a game provided from the game web site in a second folder of the file manager application. Accordingly, it is possible to easily access the game portal web site and the game pages to play the games while operating in the file manager application. | 01-15-2009 |
20100054507 | FILM SPEAKER - A film speaker is provided. The film speaker includes: a piezoelectric film oscillating by receiving a voltage corresponding to a sound signal from a sound signal supply unit; a plurality of carbon nanotube films formed on both sides of the piezoelectric film; and a plurality of electrodes connected to the plurality of carbon nanotube films, receiving the voltage corresponding to the sound signal from the sound signal supply unit, and applying the voltage to the plurality of carbon nanotube films. | 03-04-2010 |
20100328328 | HYBRID ELECTRIC DEVICE USING PIEZO-ELECTRIC POLYMER SUBSTRATE AND ITS FABRICATION METHOD - The present invention relates to an integrated, composite hybrid electric device in which various devices are formed as a single unit on one flexible substrate, and a fabrication method thereof. More particularly, the present invention a hybrid electric device in which a display device, a vibration-generating (or vibration-sensing) device, and a non-volatile memory device are formed on a single flexible piezoelectric polymer substrate into a single unit by using a flexible piezoelectric polymer substrate whose both surfaces are thinly deposited with a patterned transparent oxidation electrode, and a fabrication method thereof. | 12-30-2010 |
20120130606 | SYSTEM AND METHOD FOR DETERMINING OIL CHANGE TIMING OF AUTOMATIC TRANSMISSION - A system and method for determining the time to change the oil of an automatic transmission includes: continuously tracing/storing oil change-related information, which serves as a basis for an oil change, from the point of time when new automatic transmission oil is provided, such as the point in time of a new car purchase or the point in time of an automatic transmission oil change; determining whether or not it is time to change the oil of the automatic transmission on the basis of the oil change-related information, a preset change reference value, an oil temperature reference value, a recommended vehicle travel mileage and the like. When it is determined to be the time to change the oil of the automatic transmission, an automatic transmission oil change signal is generated to inform a driver of the necessity of changing the oil of the automatic transmission. | 05-24-2012 |
Patent application number | Description | Published |
20100238152 | PLASMA DISPLAY DEVICE - A method of driving a plasma display panel (PDP) and a plasma display device using the same are provided. In the plasma display device, a plurality of scan electrodes formed on the PDP are divided into first and second groups to supply scan signals. When a scan bias voltage is higher in a first subfield in first and second subfields, lowermost voltages of reset signals are higher in the second subfield. According to the plasma display device, when the plurality of scan electrodes are divided into at least two groups to be driven, the lowermost voltages of the reset signals are controlled in accordance with a scan bias voltage so that it is possible to reduce address erroneous discharge in accordance with the loss of wall charges, to prevent the generation of brilliant points, and to improve the picture quality of a displayed image. | 09-23-2010 |
20100238155 | PLASMA DISPLAY DEVICE - A plasma display device is provided. In the plasma display device, a plurality of scan electrodes are divided into one or more scan electrode groups, and different driving signals are applied to the scan electrode groups. More specifically, different scan bias voltages are applied to the scan electrodes during a scan period, and different signals are applied to the scan electrodes during a set-down period of a reset period. Therefore, it is possible to stabilize an address discharge in scan electrodes to which scan signals are applied late. | 09-23-2010 |
20100265240 | PLASMA DISPLAY DEVICE - A plasma display device is provided. The plasma display device includes a plasma display panel (PDP) which has an upper substrate, a lower substrate, a plurality of scan electrodes and a plurality of sustain electrodes that are disposed on the upper substrate, and a plurality of address electrodes that are disposed on the lower substrate; and a driving unit which applies driving signals to the scan electrodes, the sustain electrodes and the address electrodes. The driving unit drives the scan electrodes in units of scan electrode groups during an address period, and applies different voltages to the scan electrodes, thereby enabling an address discharge to be stably performed. | 10-21-2010 |
20100302224 | PLASMA DISPLAY DEVICE - A plasma display device is provided. In the plasma display device, a plurality of scan electrodes are divided into one or more scan electrode groups, and different driving signals are applied to the scan electrode groups. More specifically, a minimum voltage detected during a set-down period of a reset period is made to be discrepant from a scan voltage, thereby reducing the amount by which wall charge is erased and stabilizing an address discharge. In addition, different driving signals are applied to a plurality of scan electrodes, and thus, it is possible to stabilize an address discharge even in scan electrodes to which a scan signal is applied late. | 12-02-2010 |
Patent application number | Description | Published |
20110049464 | Resistive random access memory device and memory array including the same - A resistive random access memory (RRAM) includes a resistive memory layer of a transition metal oxide, such as Ni oxide, and is doped with a metal material. The RRAM may include at least one first electrode, a resistive memory layer on the at least one first electrode, the resistive memory layer including a Ni oxide layer doped with at least one element selected from a group consisting of Fe, Co, and Sn, and at least one second electrode on the resistive memory layer. The RRAM device may include a plurality of first electrodes and a plurality of second electrodes, and the resistive memory layer may be between the plurality of first electrodes and the plurality of second electrodes. | 03-03-2011 |
20110147696 | Resistive random access memory devices and resistive random access memory arrays having the same - A resistive random access memory (RRAM) devices and resistive random access memory (RRAM) arrays are provided, the RRAM devices include a first electrode layer, a variable resistance material layer formed of an oxide of a metallic material having a plurality of oxidation states, an intermediate electrode layer on the variable resistance material layer and formed of a conductive material having a lower reactivity with oxygen than the metallic material, and a second electrode layer on the intermediate electrode layer. The RRAM arrays include at least one of the aforementioned RRAM devices. | 06-23-2011 |
20110161605 | Memory devices and methods of operating the same - A memory device includes a memory cell. The memory cell includes: a bipolar memory element and a bidirectional switching element. The bidirectional switching element is connected to ends of the bipolar memory element, and has a bidirectional switching characteristic. The bidirectional switching element includes: a first switching element and a second switching element. The first switching element is connected to a first end of the bipolar memory element and has a first switching direction. The second switching element is connected to a second end of the bipolar memory element and has a second switching direction. The second switching direction is opposite to the first switching direction. | 06-30-2011 |
20110220860 | Bipolar memory cells, memory devices including the same and methods of manufacturing and operating the same - Bipolar memory cells and a memory device including the same are provided, the bipolar memory cells include two bipolar memory layers having opposite programming directions. The two bipolar memory layers may be connected to each other via an intermediate electrode interposed therebetween. The two bipolar memory layers may have the same structure or opposite structures. | 09-15-2011 |
20110310652 | Variable resistance devices, semiconductor devices including the variable resistance devices, and methods of operating the semiconductor devices - Methods of operating semiconductor devices that include variable resistance devices, the methods including writing first data to a semiconductor device by applying a reset pulse voltage to the variable resistance device so that the variable resistance device is switched from a first resistance state to a second resistance state, and writing second data to the semiconductor device by applying a set pulse voltage to the variable resistance device so that the variable resistance device is switched from the second resistance state to the first resistance state to the second resistance state. The reset pulse voltage is higher than the set pulse voltage, and a resistance in the second resistance state is greater than in the first resistance state | 12-22-2011 |
20120018695 | Non-Volatile Memory Element And Memory Device Including The Same - Example embodiments, relate to a non-volatile memory element and a memory device including the same. The non-volatile memory element may include a memory layer having a multi-layered structure between two electrodes. The memory layer may include first and second material layers and may show a resistance change characteristic due to movement of ionic species therebetween. The first material layer may be an oxygen-supplying layer. The second material layer may be an oxide layer having a multi-trap level. | 01-26-2012 |
20120032132 | Nonvolatile Memory Elements And Memory Devices Including The Same - Nonvolatile memory elements may include a first electrode, a second electrode, a first buffer layer, a second buffer layer and a memory layer. The memory layer may be between the first and second electrodes. The first butter layer may be between the memory layer and the first electrode. The second buffer layer may be between the memory layer and the second electrode. The memory layer may be a multi-layer structure including a first material layer and a second material layer. The first material layer may include a first metal oxide which is of the same group as, or a different group from, a second metal oxide included in the second material layer. | 02-09-2012 |
20120161821 | VARIABLE RESISTANCE DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE VARIABLE RESISTANCE DEVICE, AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE - A method of operating a semiconductor device that includes a variable resistance device, the method including applying a first voltage to the variable resistance device so as to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different from the first resistance value; sensing first current flowing through the variable resistance device to which the first voltage is applied; determining whether the first current falls within a predetermined range of current; and if the first current does not fall within the first range of current, applying an additional first voltage that is equal to the first voltage to the variable resistance device. | 06-28-2012 |
20120230080 | Variable Resistance Device, Semiconductor Device Including The Variable Resistance Device, And Method Of Operating The Semiconductor Device - According to an example embodiment, a method of operating a semiconductor device includes applying a first voltage to the variable resistance device so as to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different from the first resistance value, sensing first current flowing through the variable resistance device to which the first voltage is applied, determining a second voltage used to change the resistance value of the variable resistance device from the second resistance value to the first resistance value based on a distribution of the sensed first current, and applying the determined second voltage to the variable resistance device. | 09-13-2012 |
20120319076 | MULTI-BIT MEMORY ELEMENTS, MEMORY DEVICES INCLUDING THE SAME, AND METHODS OF MANUFACTURING THE SAME - In one embodiment, the memory element may include a first electrode, a second electrode spaced apart from the first electrode, a memory layer between the first electrode and the second electrode, and an auxiliary layer between the memory layer and the second electrode. The auxiliary layer provides a multi-bit memory characteristic to the memory layer. | 12-20-2012 |
20130043451 | Nonvolatile Memory Elements And Memory Devices Including The Same - Nonvolatile memory elements and memory devices including the nonvolatile memory elements. A nonvolatile memory element may include a memory layer between two electrodes, and the memory layer may have a multi-layer structure. The memory layer may include a base layer and an ionic species exchange layer and may have a resistance change characteristic due to movement of ionic species between the base layer and the ionic species exchange layer. The ionic species exchange layer may have a multi-layer structure including at least two layers. The nonvolatile memory element may have a multi-bit memory characteristic due to the ionic species exchange layer having the multi-layer structure. The base layer may be an oxygen supplying layer, and the ionic species exchange layer may be an oxygen exchange layer. | 02-21-2013 |
20130051125 | METHOD OF OPERATING SEMICONDUCTOR DEVICE INCLUDING VARIABLE RESISTANCE DEVICE - According to an example embodiment, a method of operating a semiconductor device having a variable resistance device includes: applying a first voltage to the variable resistance device to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different from the first resistance value; sensing a first current flowing through the variable resistance device to which the first voltage is applied; determining a second voltage used for changing the variable resistance device from the second resistance value to the first resistance value, based on a dispersion of the sensed first current; and applying the determined second voltage to the variable resistance device. | 02-28-2013 |
20130051164 | NONVOLATILE MEMORY DEVICES AND METHODS OF DRIVING THE SAME - A method of driving a nonvolatile memory device including applying a reset voltage to a unit memory cell, reading a reset current of the unit memory cell, confirming whether the reset current is within a first current range, if the reset current is not within the first current range, changing the reset voltage and applying a changed reset voltage or applying again the reset voltage to the unit memory cell after applying a set voltage to the unit memory cell, if the reset current is within the first current range, confirming whether a difference between the present reset current and an immediately previous set current is within a second current range, and, if the difference is not within the second current range, applying the reset voltage or applying again the reset voltage to the unit memory cell after applying a set voltage to the unit memory cell. | 02-28-2013 |
20130058153 | SEMICONDUCTOR DEVICES INCLUDING VARIABLE RESISTANCE ELEMENTS AND METHODS OF OPERATING SEMICONDUCTOR DEVICES - In a method of operating a semiconductor device, a resistance value of a variable resistance element is changed from a first resistance value to a second resistance value by applying a first voltage to the variable resistance element; and a first current that flows through the variable resistance element is sensed. A second voltage for changing the resistance value of the variable resistance element from the second resistance value to the first resistance value is modulated based on a dispersion of the first current, and the first voltage is re-applied to the variable resistance element based on a dispersion of the first current. | 03-07-2013 |
20130121060 | NON-VOLATILE MEMORY ELEMENTS AND MEMORY DEVICES INCLUDING THE SAME - Non-volatile memory elements, memory devices including the same, and methods for operating and manufacturing the same may include a memory layer between a first electrode and a second electrode spaced apart from the first electrode. The memory layer may include a first material layer and a second material layer, and may have a resistance change characteristic due to movement of ionic species between the first material layer and the second material layer. At least the first material layer of the first and second material layers may be doped with a metal. | 05-16-2013 |
20130320286 | SWITCHING ELEMENTS AND DEVICES, MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A switching element includes: a first electrode; a second electrode; and a silicon-containing chalconitride layer between the first electrode and the second electrode. A switching device includes: a threshold switch material layer between a first electrode and a second electrode. The threshold switch material layer includes a cationic metal element, a chalcogen element, a silicon element and a nitrogen element. A memory device include: a plurality of first wirings arranged in parallel with each other; a plurality of second wirings crossing the first wirings, and arranged in parallel with each other; and a memory cell formed at each intersection of the plurality of first wirings and the plurality of second wirings. The memory cell includes a laminate having a silicon-containing chalconitride layer, an intermediate electrode, and a memory layer. | 12-05-2013 |
20150028458 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer. | 01-29-2015 |
20150061030 | SEMICONDUCTOR STRUCTURE INCLUDING METAL SILICIDE BUFFER LAYERS AND METHODS OF FABRICATING THE SAME - Provided are semiconductor structures and methods of fabricating the same. The semiconductor structure includes a silicon substrate, at least one semiconductor layer that is grown on the silicon substrate and has a lattice constant in a range from about 1.03 to about 1.09 times greater than that of the silicon substrate, and a buffer layer that is disposed between the silicon substrate and the semiconductor layer and includes a metal silicide compound for lattice matching with the semiconductor layer. Related fabrication methods are also discussed. | 03-05-2015 |
20150061088 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer. | 03-05-2015 |
20150179787 | GROUP III-V SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are group III-V semiconductor transistors and methods of manufacturing the same. The method includes forming a group III-V semiconductor channel layer on a substrate, forming a gate insulating layer covering the group III-V semiconductor channel layer, and forming a protection layer including sulfur between the group III-V semiconductor channel layer and the gate insulating layer by annealing the substrate under a sulfur atmosphere. | 06-25-2015 |
Patent application number | Description | Published |
20100135660 | OPTICAL LINE TERMINAL IN GIGABIT PASSIVE OPTICAL NETWORK AND METHOD FOR TRANSMITTING BROADCAST FRAME USING THE SAME - Disclosed are an optical line terminal in a gigabit passive optical network and a method for transmitting a broadcast frame using the same. The optical line terminal allocates second port identifiers to optical network units such that a broadcast frame is prevented from being retransmitted to an optical network unit which has transmitted the broadcast frame to the optical line terminal. | 06-03-2010 |
20100135665 | BURST MODE OPTICAL REPEATER - A burst mode optical repeater is provided. The burst mode optical repeater receives optical signals, which are transmitted from a plurality of optical network units (ONUs) in a passive optical network (PON) to a central office using a time division multiplexing access (TDMA) method, and relays the received optical signals using an optical-electrical-optical (OEO) method. Since the burst mode optical repeater can be installed anywhere between an optical line terminal (OLT) and the ONUs, the number of subscribers and transmission range that can be supported by a corresponding network can be increased. | 06-03-2010 |
20100135666 | CLOCK PHASE ALIGNING APPARATUS FOR BURST-MODE DATA - Disclosed is a clock phase aligning apparatus capable of synchronizing a clock signal in the middle of an upstream burst mode data bit in an optical line terminal of a passive optical network. The clock phase aligning apparatus effectively aligns a phase of a clock signal with a phase of data during an overhead period of burst mode packet data through an over-sampling scheme and a digital scheme. Burst mode data signals are subject to an over-sampling through a high speed continuous mode analog circuit and then converted into low speed parallel signals through a parallel conversion unit. Such low speed parallel signals are processed with respect to sampling patterns through a digital look-up scheme in a logic circuit device such that the phase of data is arranged with the phase of a clock signal during a limited bit stream specified in a burst mode preamble timing. | 06-03-2010 |
20100221006 | APPARATUS AND METHOD FOR EFFICIENT BANDWIDTH ALLOCATION ON TIME DIVISION MULTIPLE ACCESS-BASED PASSIVE OPTICAL NETWORK (TDMA-PON) - Provided are an apparatus and method for efficiently and dynamically allocating a bandwidth on a Time Division Multiple Access-based Passive Optical Network (TDMA PON). The dynamic bandwidth allocation apparatus for uplink data transmission of a plurality of Optical Network Units (ONUs) including a plurality of class queues corresponding to Transmission Container (T-CONT) types, the plurality of ONUs connected to an Optical Line Terminal (OLT) on a Passive Optical Network (PON), includes: a class queue information storage unit storing information regarding a bandwidth allocation period and an allocatable bandwidth amount for each T-CONT type; an allocation check table unit checking the bandwidth allocation period for the T-CONT type received from the class queue information storage unit, and determining an allocatable bandwidth amount for the T-CONT type; and a bandwidth allocation unit allocating an uplink bandwidth to the T-CONT type with reference to the bandwidth allocation period and the allocatable bandwidth amount for the T-CONT type, and re-allocating to each ONU an uplink bandwidth remaining after allocating a total uplink bandwidths to all T-CONT types. | 09-02-2010 |
20100260498 | OPTICAL NETWORK TERMINAL OF THE GIGABIT PASSIVE OPTICAL NETWORK AND FRAME TREATMENT METHOD OF THE ONT - A gigabit passive optical network (GPON) system for fiber to the home (FTTH) service must provide a down-stream data rate of an optical band to provide IPTV service with hundreds of channels to subscribers, and must be able to provide an upstream data rate of an optical band using a currently available BM-IC chip. A currently available BM-IC chip for a GPON has 1.244 Gbps and 2.488 Gbps modes. Accordingly, an optical network terminal (ONT) for a GPON that is capable of providing a downstream transmission band of 10-Gbps and an upstream transmission band of 1.244 Gbps or 2.488 Gbps, and a method for processing an upstream frame in the terminal, are provided. The GPON ONT can provide 20 Mbps, high-definition IPTV service with 500 channels and can provide both upstream data rates of 1.244 Gbps and 2.488 Gbps according to a user's selection without using an additional device. | 10-14-2010 |
20100272259 | METHOD FOR FILTERING OF ABNORMAL ONT WITH SAME SERIAL NUMBER IN A GPON SYSTEM - Disclosed is a method of registering only an authorized optical network terminal among a plurality of optical network terminals with the same serial number, in an optical line terminal, using a public key encryption algorithm, in a Gigabit Passive Optical Network (GPON). According to an exemplary aspect, a GPON system encrypts a physical layer OAM message transmitted/received for serial number registration of an optical network terminal, using a key distributed according to a public key encryption algorithm, and authenticates registration of the optical network terminal using the encrypted physical layer OAM message. Accordingly, it is possible to securely authenticate registration of an authorized optical network terminal and block registration of unauthorized optical network terminals. | 10-28-2010 |
20110129235 | BURST-MODE OPTICAL SIGNAL RECEIVER - A burst-mode optical receiver is provided. The burst-mode optical receiver includes a preamplifier, a post-amplifier integrated into one body together with the preamplifier, and an operation controller for controlling operation of the preamplifier and the post-amplifier using an external reset signal input from a single external reset input terminal. As a result, it is possible to implement a burst-mode receiver for a gigabit-capable passive optical network (GPON) in which a preamplifier unit and a post-amplifier unit are integrated. | 06-02-2011 |
20120045210 | OPTICAL SUBSCRIBER NETWORK - An optical subscriber network for power reduction is provided. The optical subscriber network may include an Optical Line Terminal (OLT) and an Optical Network Terminal (ONT). The OLT may manage a plurality of ONTs by classifying the plurality of ONTs into a sleep group, and may multicast a sleep allowance message only to ONTs included in a predetermined sleep group. | 02-23-2012 |
20120163818 | PASSIVE OPTICAL NETWORK APPARATUS FOR TRANSMITTING OPTICAL SIGNAL - Disclosed herein are a remote node and a telephone station terminal in a passive optical network (PON). The remote node includes an optical circulator that transmits downlink signals input from a downlink optical backbone network to a wavelength distributor and transmits uplink signals input from the wavelength distributor to an uplink optical backbone network different from a downlink optical backbone network; and a wavelength distributor that distributes the downlink signal input from the optical circulator into a plurality of wavelengths to be connected to an optical distribution network and connects the uplink signals input from the optical distribution network to the optical circulator. | 06-28-2012 |
20120315046 | PASSIVE OPTICAL NETWORK (PON)-BASED SYSTEM AND METHOD FOR PROVIDING HANDOVER AMONG OPTICAL NETWORK TERMINALS (ONTS) - A Passive Optical Network (PON)-based system and method for providing handover between Optical Network Terminals (ONTs) are provided. The PON-based system may include an Optical Line Terminal (OLT), and an ONT to relay communication between the OLT and a mobile terminal. When the mobile terminal is connected to the ONT, the ONT may transmit a WiFi location update alarm message to the OLT, and the OLT may update a Look-Up Table (LUT) in response to the WiFi location update alarm message. | 12-13-2012 |
20130071111 | APPARATUS AND METHOD FOR MANAGING DYNAMIC BANDWIDTH ALLOCATION TO SUPPORT LOW-POWER MODE IN PASSIVE OPTICAL NETWORK (PON) - An apparatus and method for managing a dynamic bandwidth allocation to support a low-power mode, in a passive optical network (PON) are provided. The apparatus may include a power saving mode managing unit to manage a power saving mode of at least one optical network unit (ONU), a bandwidth allocation parameter storage unit to store a bandwidth allocation parameter used for a power saving mode, and to maintain the stored bandwidth allocation parameter, and a dynamic bandwidth allocating unit to provide bandwidth allocation information to the at least one ONU, when the stored bandwidth allocation parameter is received. | 03-21-2013 |
20150244454 | FAST PROTECTION SWITCHING METHOD FOR PASSIVE OPTICAL NETWORK - A fast protection switching method for a Passive Optical Network (PON). When performing protection switching from an operation link (an operation network) to a protection link (a protection network) in a PON, the fast protection switching method enables rapidly updating Equalization Delay (EqD) values, even if the EqD values are different for Optical Network Terminals (ONTs) of varying distances. | 08-27-2015 |