Patent application number | Description | Published |
20120170364 | Method Of Programming A Nonvolatile Memory Device - In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data. | 07-05-2012 |
20130088928 | MEMORY SYSTEM COMPRISING NON-VOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory device comprises a first memory region and a second memory region. The nonvolatile memory device is programmed by storing program data in the first memory region, performing coarse programming and fine programming to store the program data in the second memory region, and in response to a read request, accessing the program data from the first memory region or the second memory region according to a fine program flag indicating whether the coarse programming has been completed. | 04-11-2013 |
20130100737 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory comprises a memory block having memory cells stacked in a three dimensional structure. The nonvolatile memory device performs an erase operation to erase a selected sub block among sub blocks of the memory block, a verification operation to determine whether program states of memory cells of an unselected sub block of the memory block have changed as a consequence of the erase operation, and a reprogramming operation to reprogram at least a portion of the unselected sub block upon determining that at least one of the program states have changed as a consequence of the erase operation. | 04-25-2013 |
20130107653 | NONVOLATILE MEMORY HAVING STACKED STRUCTURE AND RELATED METHOD OF OPERATION | 05-02-2013 |
20130138869 | NONVOLATILE MEMORY AND MEMORY DEVICE INCLUDING THE SAME - A nonvolatile memory has a first memory block including a plurality of sub memory blocks stacked in a direction perpendicular to a substrate, and a second memory block including a plurality of sub memory blocks stacked in a direction perpendicular to the substrate, the second memory block being parallel to the first memory block. Management data unchanged after it is programmed once is stored in at least one sub memory block of the first memory block and main data is stored in sub memory blocks of the second memory block. Meta data may be stored in a sub memory block of the first memory block of in any memory block that does not contain the management data. | 05-30-2013 |
20140047167 | NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING SUSPENSION OF COMMAND EXECUTION OF THE SAME - A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer, and control logic. The memory cell array includes memory cells connected to word lines and bit lines, the memory cell array being configured to store data. The row decoder is configured to selectively activate a string selection line, a ground selection line, and the word lines of the memory cell array. The page buffer is configured to temporarily store external data and to apply a predetermined voltage to the bit lines according to the stored data during a program operation, and to sense data stored in selected memory cells using the bit lines during a read operation or a verification operation. The control logic is configured to control the row decoder and the page buffer. During execution of commands, when a request to suspend the execution of the commands is retrieved, chip information is backed up to a storage space separate from the control logic. | 02-13-2014 |
20140104955 | PROGRAMMING NONVOLATILE MEMORY DEVICE USING PROGRAM VOLTAGE WITH VARIABLE OFFSET - A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias. | 04-17-2014 |
20140247657 | METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE - In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data. | 09-04-2014 |
20150049548 | Read Methods for Non-Volatile Memory Devices and Related Non-Volatile Memory Devices - Read methods for a non-volatile memory device are provided. The read method includes sensing memory cells in an Nth program state using original read voltages of an Nth level, where N is a natural number greater than 2, counting the number of memory cells in the Nth program state according to the sensing result, and when the number of memory cells in the Nth program state is greater than a reference number, sensing memory cells in first to Nth program states using adjusted read voltages of first to Nth levels. The adjusted read voltages are obtained by adding offset voltages to the original read voltages. | 02-19-2015 |