Patent application number | Description | Published |
20100136433 | METHOD OF PREPARING SPHERICAL SHAPE POSITIVE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY - The present invention relates to a process of preparing a spherically-shaped positive active material for a lithium secondary battery, comprising: (a) uniformly dissolving a raw material mixture comprising a lithium-based compound, a transition metal, phosphate-based compound and a carbon source in deionized water; (b) preparing a high density spherically-shaped precursor by rapidly freezing the mixed solution in a freeze granulator and sublimating the frozen mixed solution; and (c) thermally treating the high density spherically-shaped precursor. | 06-03-2010 |
20110027658 | METHOD FOR PREPARING CROSS-LINKED CERAMIC-COATED SEPARATOR CONTAINING IONIC POLYMER, CERAMIC-COATED SEPARATOR PREPARED BY THE METHOD, AND LITHIUM SECONDARY BATTERY USING THE SAME - The present invention provides method for preparing a cross-linked ceramic-coated separator containing an ionic polymer, a ceramic-coated separator prepared by the method, and a lithium secondary battery using the same. According to preferred methods for preparing a cross-linked ceramic-coated separator, a coating material containing ceramic particles for improving thermal and mechanical characteristics, a functional inorganic compound for improving cycle characteristics and high rate characteristics of a battery, and an ionic polymer for bonding the ceramic particles and the functional inorganic compound on a porous membrane substrate is coated on the porous membrane substrate and subjected to chemical cross-linking. | 02-03-2011 |
20110059345 | BATTERY PACK - The present invention features a battery pack, that is provided to supply electricity to a variety of electric parts, such as a drive motor, installed in an environment friendly electric vehicle such as a fuel cell vehicle or a hybrid electric vehicle. Preferably, the battery pack is configured to stack cell assemblies. Each cell assembly includes a cell case. The cell case includes windows in opposite surfaces thereof such that unit cells are exposed, and recesses in opposite long lateral faces thereof such that the windows communicate with an outside. The windows and the recesses define cooling passages between the stacked cell assemblies. | 03-10-2011 |
20120012798 | Positive electrode material for lithium secondary battery and method for manufacturing the same - The present invention provides a positive electrode material for a lithium secondary battery comprising a compound represented by the following Formula 1: | 01-19-2012 |
20120141877 | ELECTRODE OF SECONDARY CELL INCLUDING POROUS INSULATING LAYER, AND MANUFACTURING METHOD THEREOF - The present invention provides a manufacturing method of a secondary cell electrode forming a porous insulating layer on at least one surface between a negative electrode and a positive electrode, including coating an electrode layer slurry on the electrode surface, coating the porous insulating layer while in a state in which the electrode layer slurry has not been dried, and simultaneously drying the electrode layer slurry and the porous insulating layer coating slurry so a binder of the porous insulating layer does not block the pores of the electrode layer. | 06-07-2012 |
Patent application number | Description | Published |
20130164511 | Thermochromic Substrate And Method Of Manufacturing The Same - A thermochromic substrate that has a thermochromic thin film, and a method of manufacturing the same. The thermochromic substrate includes a base substrate, an oxide or nitride thin film formed on the base substrate, a vanadium dioxide (VO | 06-27-2013 |
20130194652 | REFLECTIVE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A reflective substrate, the transmittance of visible light of which is improved, and a method of manufacturing the same. The reflective substrate includes a glass substrate, an oxide or nitride film formed on the glass substrate, and vanadium dioxide (VO | 08-01-2013 |
20130335803 | Thermochromic Window - A thermochromic window that can effectively insulate heat when warming is conducted in winter. The thermochromic window that includes a substrate, a thermochromic thin film formed on the substrate, and a transparent conductive film formed on at least one surface of the upper surface and the undersurface of the thermochromic thin film. The emissivity of the transparent conductive film is lower than the emissivity of the thermochromic thin film. | 12-19-2013 |
20140002886 | THERMOCHROMIC WINDOW DOPED WITH DOPANT AND METHOD OF MANUFACTURING THE SAME | 01-02-2014 |
Patent application number | Description | Published |
20110006662 | Display Apparatus and Method for Manufacturing the Same - An electro-optic device is inserted and mounted into the internal space of the multi-layered member. Herein, the multi-layered member includes the first and second plates disposed to be separated from and facing each other. At least one of the first and second plates is manufactured with a transparent material to transmit light that is generated from the electro-optic device. Among the first and second plates of the multi-layered member, a plate corresponding to the size of a display apparatus to be manufactured is used. Consequently, by inserting and mounting a small electro-optic device into the internal space of the multi-layered member that is manufactured in a large area, a large-area display apparatus can be manufactured even without using a large-size deposition apparatus and a large-area substrate. Accordingly, the manufacturing cost of the large-area display apparatus can be saved. | 01-13-2011 |
20130201133 | METHOD AND APPARATUS FOR INPUTTING A KEY IN A PORTABLE TERMINAL - A method for inputting a key in a portable terminal is provided. The method includes setting a font to be used when a handwriting is converted into a text, receiving an input of the handwriting of a user by using a touch pen of a touch screen, and recognizing the input handwriting to convert the input handwriting into the text in the set font. | 08-08-2013 |
20140184969 | THIN FILM TRANSISTOR SUBSTRATE AND LIQUID CRYSTAL DISPLAY INCLUDING THE THIN FILM TRANSISTOR SUBSTRATE - A thin film transistor substrate a display area that includes pixels connected to gate lines and data lines crossing the gate lines, a non-display area disposed adjacent to the display area, data pads disposed in the non-display area and each being connected to a first end of a corresponding data line of the data lines, first transistors disposed in the non-display area and each being connected to a second end of the corresponding data line of the data lines, OS pads connected to the second end of the data lines, and repair lines disposed in the non-display area along a vicinity of the display area and arranged while interposing the first transistors therebetween. The OS pads are overlapped with the first transistors and the repair lines. | 07-03-2014 |
20150212375 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes: a gate line including a gate electrode; a data line including a source electrode; a drain electrode; an organic layer on the gate and data lines and the drain electrode, and a first opening defined therein; a first electrode on the organic layer, and a second opening defined therein; and a passivation layer on the first electrode, and a contact hole defined therein exposing the drain electrode. An interval taken in a first direction between a first edge of the gate electrode, the first edge parallel to a second direction in which the gate line is extended and which is different than the first direction, and a second edge of the first electrode second opening, the second edge parallel to the second direction and adjacent to the gate electrode first edge is 0 micrometer to about 6 micrometers. | 07-30-2015 |
20150364102 | DISPLAY APPARATUS - A display apparatus includes a first substrate including a channel-forming area, a second substrate facing the first substrate, a thin-film transistor disposed on the first substrate, a pixel electrode electrically connected to the thin-film transistor, a gate line disposed on the first substrate and electrically connected to the thin-film transistor, a data line electrically connected to the thin-film transistor and divided into at least two portions such that the channel-forming area is disposed between the two portions of the data line, and a connection portion electrically connecting the two portions of the data line to each other, in which the thin-film transistor includes a gate electrode branched from the gate line and overlapping the channel-forming area, a semiconductor pattern overlapping the gate electrode and contacting the two portions of the data line so that the channel-forming area is disposed in the semiconductor pattern, and a drain electrode electrically connected to the pixel electrode and overlapping the semiconductor pattern. | 12-17-2015 |
Patent application number | Description | Published |
20150052310 | CACHE DEVICE AND CONTROL METHOD THEREOF - A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set. | 02-19-2015 |
20150106551 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The semiconductor device may include a wear leveling controller configured to select a first physical address of the semiconductor memory device to remap a logical address corresponding to the first physical address of the semiconductor memory device to a second physical address of the semiconductor memory device, and to adjust the first interval. | 04-16-2015 |
20150134876 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device may include: a data storage unit comprising a plurality of channels each having a plurality of nonvolatile memory devices; and a control unit configured to control a garbage collection operation of selecting a first block included in a first channel as a victim block and copying first data included in the first block into a second block included in a second channel that is selected. | 05-14-2015 |
20150347290 | SEMICONDUCTOR DEVICE - A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array. | 12-03-2015 |
Patent application number | Description | Published |
20110158532 | APPARATUS FOR DETECTING TEXT RECOGNITION REGION AND METHOD OF RECOGNIZING TEXT - A text recognition region detecting apparatus and a text recognition method are provided. A text recognition region is detected by expanding a region based on a user-specified position that is input through a simple manipulation by a user. A text recognition is performed on the detected text recognition region, thereby relieving a user from having to precisely input the text region and ensuring the user's convenience. | 06-30-2011 |
20110161637 | APPARATUS AND METHOD FOR PARALLEL PROCESSING - An apparatus and method for parallel processing in consideration of degree of parallelism are provided. One of a task parallelism and a data parallelism is dynamically selected while a job is processed. In response to a task parallelism being selected, a sequential version code is allocated to a core or processor for processing a job. In response to a data parallelism being selected, a parallel version code is allocated to a core a processor for processing a job. | 06-30-2011 |
20140083755 | LAMINATED CHIP ELECTRONIC COMPONENT, BOARD FOR MOUNTING THE SAME, AND PACKING UNIT THEREOF - A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer. | 03-27-2014 |
20150348711 | MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON - A multilayer ceramic capacitor may include: a ceramic body; a first internal electrode is spaced apart from first and second end surfaces by a predetermined distance and includes first and second lead portions which are spaced apart from each other and exposed to a first main surface; and a second internal electrode is spaced apart from the first and second end surfaces by a predetermined distance and includes a third lead portion positioned between the first and second lead portions and exposed to the first main surface. The ceramic body may further include first and second dummy electrodes, a first dummy electrode being disposed on a dielectric layer on which the first internal electrode is disposed, and a second dummy electrode being disposed on a dielectric layer on which the second internal electrode is disposed. | 12-03-2015 |
20160005480 | NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A method for operating the 3D NAND device includes providing first and second dies and initial read levels for the first and second dies, changing the initial read level for the first die to a first read level based on a first offset that is calculated in consideration of elapsed time from a time point when a program for the first die is completed, changing the initial read level for the second die to a second read level based on a second offset that is calculated in consideration of elapsed time from a time point when a program for the second die is completed, and reading data stored in the first die using the first read level or reading data stored in the second die using the second read level. | 01-07-2016 |
Patent application number | Description | Published |
20090001503 | SEMICONDUCTOR DEVICE HAVING FLOATING BODY ELEMENT AND BULK BODY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate is provided. A first buried dielectric layer interposed between the first buried patterns and the substrate and between the first buried patterns and the first active patterns is provided. | 01-01-2009 |
20090108318 | Integrated Circuit Semiconductor Device Including Stacked Level Transistors and Fabrication Method Thereof - An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer. | 04-30-2009 |
20090253244 | Nonvolatile Memory Devices Having Gate Structures Doped by Nitrogen and Methods of Fabricating the Same - Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein. | 10-08-2009 |
20100285644 | Methods of Forming Semiconductor Devices Having Recessed Channels - A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided. | 11-11-2010 |
20110266608 | NONVOLATILE MEMORY DEVICES HAVING GATE STRUCTURES DOPED BY NITROGEN - Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein. | 11-03-2011 |
20120305997 | Semiconductor Devices Having Recessed Channels - A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided. | 12-06-2012 |