Patent application number | Description | Published |
20090138743 | METHOD AND APPARATUS FOR SECURE COMMUNICATION BETWEEN CRYPTOGRAPHIC SYSTEMS USING REAL TIME CLOCK - Provided are a method and apparatus for secure communication between cryptographic systems using a Real Time Clock (RTC). The method and apparatus allow a transmitting cryptographic system to transfer partial RTC data and a receiving cryptographic system to restore entire RTC data, thereby minimizing data to be transferred between the cryptographic systems. The method includes: calculating a largest RTC deviation between a transmitting cryptographic system and a receiving cryptographic system; calculating the smallest number of bits of partial data on an RTC required for restoring entire data on the RTC on the basis of the calculated largest RTC deviation; calculating the partial RTC data on the basis of the calculated smallest number of bits of the partial RTC data; and transferring the calculated partial RTC data to the receiving cryptographic system. | 05-28-2009 |
20130336480 | LOW-POWER ENCRYPTION APPARATUS AND METHOD - An encryption apparatus and method that provide a mobile fast block cipher algorithm that supports low-power encryption. The encryption apparatus includes a user interface unit, a key scheduler unit, an initial conversion unit, a round function processing unit, and a final conversion unit. The user interface unit receives plain text to be encrypted and a master key. The key scheduler unit generates a round key from the master key. The initial conversion unit generates initial round function values from the plain text. The round function processing unit repeatedly processes a round function using the round key and the initial round function values. The final conversion unit generates ciphertext from the resulting values of the round function processed in a final round by the round function processing unit. | 12-19-2013 |
20140355755 | APPARATUS AND METHOD FOR PERFORMING COMPRESSION OPERATION IN HASH ALGORITHM - An apparatus and method for performing a compression operation in a fast message hash algorithm, which receive a 512-bit message and 512-bit chaining variable data, repeatedly calculate a 128-bit register-based step function, and then produce updated 512-bit chaining variable data. For this, the apparatus for performing a compression operation in a hash algorithm includes a message extension unit for receiving a message and generating a plurality of extended messages. A chaining variable initial conversion unit receives chaining variable data and converts the chaining variable data into initial state data. A step function operation unit repeatedly calculates a step function based on the initial state data and the plurality of extended messages and produces final state data. A chaining variable final conversion unit generates updated chaining variable data from the chaining variable data using the final state data, and outputs the updated chaining variable data. | 12-04-2014 |
20150032704 | APPARATUS AND METHOD FOR PERFORMING COMPRESSION OPERATION IN HASH ALGORITHM - An apparatus and method for performing a compression operation in a hash algorithm are provided. The apparatus includes an interface unit, a message extension unit, a chain variable initial conversion unit, a compression function computation unit, and a chain variable final conversion unit. The interface unit receives a message and chain variable data. The message extension unit generates a plurality of extended messages from the message. The chain variable initial conversion unit converts the chain variable data into initial state data for a compression function. The compression function computation unit repeatedly computes extended message binding and step functions based on the initial state data and the plurality of extended messages, and performs combination with a final extended message, thereby computing final state data. The chain variable final conversion unit generates and outputs chain variable data, into which the chain variable data has been updated, using the final state data. | 01-29-2015 |
20150078644 | METHOD OF GENERATING MAGNETIC RESONANCE IMAGE, METHOD OF ACQUIRING PHASE INFORMATION OF PHASE CONTRAST IMAGE, METHOD OF ACQUIRING PHASE INFORMATION OF SUSCEPTIBILITY WEIGHTED IMAGE, AND APPARATUS FOR GENERATING MAGNETIC RESONANCE IMAGE - Disclosed are a magnetic resonance (MR) image generating method and apparatus that perform imaging on an MR image by using a radio frequency (RF) multi-coil which includes a plurality of channel coils. The MR image generating method includes generating a plurality of pieces of K-space completion data which respectively correspond to the plurality of channel coils and converting the plurality of pieces of K-space completion data to a frequency domain in order to generate a plurality of pieces of image data, combining the plurality of pieces of image data in order to acquire an MR image, and acquiring phase information which relates to the MR image based on the plurality of pieces of image data and the plurality of pieces of K-space completion data. | 03-19-2015 |
20150117735 | PARALLEL IMAGE RECONSTRUCTION USING FILTER BANKS BASED ON LOW-FREQUENCY PART OF K-SPACE SIGNALS - A method for a parallel image reconstruction is disclosed. The method includes (a) acquiring image information by channel via parallel coils in a magnetic resonance imaging (MRI) scanner; (b) extracting low-frequency signals from the image information; (c) reconstructing low-frequency images from the low-frequency signals; (d) generating filter banks by using the low-frequency images; and (f) reconstructing a final image by using the filter banks. The generating of the filter banks includes separately generating low-frequency image information for reconstruction of magnitude information and low-frequency image information for reconstruction of phase information, and then separately generating a filter for reconstruction of the magnitude information and a filter for reconstruction of the phase information. | 04-30-2015 |
Patent application number | Description | Published |
20120013418 | APPARATUS AND METHOD FOR DETECTING TRANSMISSION AND RECEPTION SIGNAL - Provided is a transmission and reception signal detecting apparatus, which includes a directional coupler and a signal detecting part. The directional coupler includes a first port and a second port. The signal detecting part is connected to the first and second ports of the directional coupler and detects an output of a first signal transmitted through the first port and an output of a second signal transmitted through the second port. The signal detecting part is connected to the first port under a first operation condition. The signal detecting part is connected to the second port under a second operation condition. | 01-19-2012 |
20120026063 | APPARATUS AND METHOD FOR MATCHING IMPEDANCE USING STANDING WAVE RATIO INFORMATION - An apparatus and method for matching impedance of an antenna by using Standing Wave Ratio (SWR) information is provided. While the impedance of the impedance matching unit is controlled, a region of a Smith chart in which initial total impedance of the impedance matching unit and the antenna is located by using an SWR calculated by an SWR operation unit, and the impedance of the impedance matching unit is controlled according to the determined region, thus correctly matching the impedance of the antenna. | 02-02-2012 |
20130063857 | MEMS VARIABLE CAPACITOR AND METHOD FOR DRIVING THE SAME - Disclosed herein is an MEMS variable capacitor and its driving method, the MEMS variable capacitor including, a first electrode, a second electrode floating over the first electrode upper part, a fixed electrode separated at the second electrode side surface, and a drifting electrode placed between the second electrode and the fixed electrode, connected to the second electrode, and physically contacting the fixed electrode by a voltage applied to the fixed electrode. | 03-14-2013 |
20130135785 | MEMS VARIABLE CAPACITOR - Disclosed is a MEMS variable capacitor, the capacitor including a first electrode, a second electrode that is floated on an upper surface of the first electrode, and a third electrode capable of variably-adjusting a capacitance value by adjusting a gap between the first electrode and the second electrode. | 05-30-2013 |
20130135786 | VARIABLE CAPACITOR AND METHOD FOR DRIVING THE SAME - Disclosed herein is a variable capacitor and its driving method, the variable capacitor including, a movable first electrode; and a second electrode formed with an insulating film, fixed in place, and its insulating film contacting the first electrode that is moved. | 05-30-2013 |
20130335037 | Apparatus and Method for Displaying State of Terminal - A device and a method are provided. In a terminal capable of at least one of a wireless charging function and a near field communication (NFC) function, the device displays operation states of the functions via an e-skin unit. Wireless charging efficiency, a charging state, and a communication state may be selectively or totally displayed to a user. | 12-19-2013 |
Patent application number | Description | Published |
20090233416 | FLASH MEMORY DEVICES COMPRISING PILLAR PATTERNS AND METHODS OF FABRICATING THE SAME - Flash memory devices include pillar patterns formed between selected pairs of floating gates and control gate extensions that penetrate between selected pairs of floating gates are provided. Methods of fabricating the flash memory devices are also provided. | 09-17-2009 |
20100109057 | Fin field effect transistor and method of fabricating the same - A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode. | 05-06-2010 |
20100155959 | Semiconductor Devices Having Narrow Conductive Line Patterns and Related Methods of Forming Such Semiconductor Devices - Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction. | 06-24-2010 |
20130040452 | Methods of Forming Semiconductor Devices Having Narrow Conductive Line Patterns - Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction. | 02-14-2013 |
20140038383 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING PHOTO KEY - A method of fabricating a semiconductor device includes providing a substrate that is divided into a first region on which a pattern layer is formed and a second region on which a photo key is formed. A silicon layer is formed on the first region and second region of the substrate. The silicon layer is patterned to form a hole exposing a photo key portion of the second region on which the photo key is formed. A buried oxide layer is formed to fill the hole exposing the photo key portion. The silicon layer is patterned by using the photo key formed under the buried oxide layer to form a silicon pattern layer. | 02-06-2014 |
20140106567 | METHODS OF FORMING FINE PATTERNS IN SEMICONDUCTOR DEVICES - Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure. | 04-17-2014 |
20140328125 | METHODS OF FORMING FINE PATTERNS IN SEMICONDUCTOR DEVICES - Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure. | 11-06-2014 |
Patent application number | Description | Published |
20110124172 | METHOD OF FORMING INSULATING LAYER AND METHOD OF MANUFACTURING TRANSISTOR USING THE SAME - Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO | 05-26-2011 |
20110237037 | Methods of Forming Recessed Channel Array Transistors and Methods of Manufacturing Semiconductor Devices - In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure. | 09-29-2011 |
20140134812 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a trench in a substrate, forming a pre-gate insulating film along side surfaces and a bottom surface of the trench, and oxidizing the pre-gate insulating film through a densification process. | 05-15-2014 |
20140367774 | Semiconductor Devices Having Partially Oxidized Gate Electrodes - Semiconductor devices are provided including a first trench in a semiconductor substrate; a first insulating film in the first trench; a first conductive film on the first insulating film, the first conductive film having upper and lower portions and filling at least a portion of the first trench; and a first work function adjustment film having first and second portions, a first lower work function adjustment film portion and a first upper work function adjustment portion. The first lower work function adjustment film portion overlaps the lower portion of the first conductive film and the first upper work function adjustment film portion overlaps the upper portion of the first conductive film between the first insulating film and the first conductive film. | 12-18-2014 |
20150060862 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line. | 03-05-2015 |
20150228786 | Semiconductor Device - A semiconductor device includes a semiconductor substrate having an active region. A gate trench is disposed to cross the active region. First and second source/drain regions are disposed in the active region at both sides of the gate trench. A gate electrode is disposed in the gate trench. A gate dielectric layer is disposed between the gate electrode and the active region. A stress pattern is disposed on the gate electrode and in the gate trench. The stress pattern has a lower residual stress than silicon nitride. | 08-13-2015 |
Patent application number | Description | Published |
20100025749 | SEMICONDUCTOR DEVICE - A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer | 02-04-2010 |
20100035425 | Integrated Circuit Devices Having Partially Nitridated Sidewalls and Devices Formed Thereby - Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer. | 02-11-2010 |
20100072545 | Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor - A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current. | 03-25-2010 |
20120282769 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING ELECTRICALLY CONDUCTIVE LAYERS THEREIN WITH PARTIALLY NITRIDATED SIDEWALLS - Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer. | 11-08-2012 |
Patent application number | Description | Published |
20140138639 | ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode includes a first electrode including a reflective metal layer of a light-reflective metal, an upper transparent conductive layer on the reflective metal layer, and an amorphous oxide layer on the upper transparent conductive layer, an organic emission layer on the first electrode, and a second electrode on the organic emission layer. | 05-22-2014 |
20140186983 | MASK, METHOD OF CLEANING THE MASK, AND METHOD OF MANUFACTURING A PLURALITY OF ORGANIC ELECTROLUMINESCENT ELEMENTS USING THE MASK - A method of cleaning a mask includes preparing a mask on which a first metal layer and a second metal layer are stacked sequentially, and lifting off the second metal layer by removing the first metal layer. | 07-03-2014 |
20150048325 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display is provided. An OLED display in accordance with an exemplary embodiment may include a substrate including a first subpixel, a second subpixel, and a third subpixel, a first electrode disposed on each of the first subpixel, the second subpixel, and the third subpixel, a second electrode facing the first electrode, a first common layer disposed on the first subpixel and the second subpixel, a first emission layer and a second emission layer disposed on the first common layer, a second common layer disposed on the third subpixel, and a third emission layer disposed on the second common layer. The first common layer may include a first doping layer and a second doping layer disposed on the first doping layer. Each of the doping layers may including a p-type dopant, and the second common layer may be formed as a single layer. | 02-19-2015 |
20150069359 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An organic light emitting display apparatus, including a first electrode; a second electrode on the first electrode, the second electrode including silver and magnesium; an organic emission layer between the first electrode and the second electrode; a metal layer between the organic emission layer and the second electrode; and a barrier layer between the organic emission layer and the second electrode. | 03-12-2015 |
20150102305 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device including a first sub-pixel, a second sub-pixel, and a third sub-pixel on a substrate; a plurality of first electrodes in the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively; a second electrode being a sub-common layer to the first sub-pixel and the second sub-pixel and facing the first electrodes of the first sub-pixel and the second sub-pixel; and a third electrode in the third sub-pixel and facing the first electrode of the third sub-pixel is disclosed. | 04-16-2015 |
20150236296 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - Provided is an organic light-emitting display apparatus that includes a substrate; a first electrode on the substrate; an intermediate layer on the first electrode and including an organic emission layer; and a second electrode that includes a first layer including a dipole material, a second layer including a material having a work function of 3.6 eV or less, and a third layer including a conductive material, wherein the first to third layers are sequentially disposed on the intermediate layer. | 08-20-2015 |
20150255744 | ORGANIC LIGHT EMITTING DIODE - An organic light emitting diode includes a first electrode including a first electrode including a reflective metal layer formed of a light-reflective metal, an upper transparent conductive layer positioned on the reflective metal layer, and a protective layer positioned on the upper transparent conductive layer; an organic emission layer positioned on the first electrode; and a second electrode positioned on the organic emission layer, wherein the upper transparent conductive layer is amorphous. | 09-10-2015 |
20150263306 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device may include a substrate; an anode on the substrate; a hole transport region on the anode; an emission layer on the hole transport region; an electron transport region on the emission layer; and a cathode on the electron transport region. The electron transport region may include an electron injection layer including a first component which is a salt chloride and a second component which is at least one metal selected from ytterbium (Yb), scandium (Sc), vanadium (V), yttrium (Y), indium (In), cerium (Ce), samarium (Sm), europium (Eu), and terbium (Tb). In addition, the cathode may contacts the electron injection layer and may include an alloy of a first cathode metal including at least one of Ag, Au, Pt, Cu, Mn, Ti, Co, Ni, and W, and a second cathode metal including least one of Yb, Sc, V, Y, In, Ce, Sm, Eu, and Tb. | 09-17-2015 |
20150364715 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device with a plurality of subpixels, each subpixel including an emission region and a non-emission region, the organic light-emitting device including a substrate; an anode on the substrate, the anode including patterns that separately correspond to respective ones of the plurality of subpixels; an organic layer on the anode, the organic layer being common to the plurality of subpixels; and a cathode on the organic layer, the cathode including a plurality of subcathodes that each correspond to at least one of the subpixels and that allow light to pass through in emission regions, wherein adjacent two of the subcathodes overlap with each other in non-emission regions. | 12-17-2015 |
Patent application number | Description | Published |
20130010667 | APPARATUS AND METHOD FOR PROVIDING MULTICAST/ BROADCAST SERVICE IN MOBILE COMMUNICATION SYSTEM - An apparatus and method for providing a multicast/broadcast service in a mobile communication system. Upon detecting an occurrence of a multicast data packet, an Internet Protocol (IP) terminal converts the multicast data packet into an alternative multicast data packet, and transmits the alternative multicast data packet to a femto Node B. Upon detecting an occurrence of a broadcast data packet, the IP terminal converts the broadcast data packet into an alternative broadcast data packet, and transmits the alternative broadcast data packet to the femto Node B. | 01-10-2013 |
20130077570 | APPARATUS AND METHOD FOR ACCESSING LOCAL NETWORK IN MOBILE COMMUNICATION SYSTEM SUPPORTING LOCAL NETWORK INTERNET PROTOCOL ACCESS SCHEME - An apparatus and method for accessing a local network in a mobile communication system supporting a Local Network Internet Protocol Access (LIPA) scheme are provided. In the method, a User Equipment (UE) transmits a radio bearer set up request packet to a router connected to a femto Node B in order to set up a radio bearer with the femto Node B, thereby the router converts the radio bearer set up request packet into a port forward radio bearer set up request packet using a port forward function, and transmits the port forward radio bearer set up request packet to the femto Node B. | 03-28-2013 |
20130137553 | WALKING TRAINING APPARATUS - Provided is a walking training apparatus including: a walking-assist robot which is worn on a lower half of a body of a walking trainee; a treadmill which has a tread plate moving at a predefined speed which the walking trainee walks on; a load pulling unit which holds a body of the walking trainee upward; and a controller which controls driving of the walking-assist robot, the treadmill, and the load pulling unit, wherein the load pulling unit includes: a harness which is worn on the body of the walking trainee; a main rope which is connected to the harness; a driving motor which operates to pull the main rope so as to pull the harness upward; and a counter-load weight plate unit which applies a counter-load to the walking trainee. Accordingly, the load pulling unit pulls a patient, and a counter-load is appropriately set according to a state of the patient or a purpose of a therapy, so that it is possible to prevent the patient from falling during the waling training, and it is possible to effectively perform rehabilitation training of the patient. | 05-30-2013 |
20140378279 | WALKING TRAINING APPARATUS - The present invention relates to a walking training apparatus. The walking training apparatus includes: a treadmill providing a bottom surface to allow a user who is training to walk to do so in a stationary position; a user counterweight unit including a counterweight, a wire, and a harness jacket, wherein the user counterweight unit lifts the user's body upward in order to reduce the load from the user's weight; a joint motion robot worn on one lower leg of the walker, wherein the joint motion robot is constituted by a hip-joint motion part, a knee-joint motion part, and an ankle-joint motion part; a joint motion robot support part supporting and coupled to the joint motion robot to reduce the load of the weight of the joint motion robot, wherein the joint motion robot support includes a horizontal movable part and a vertical movable part for moving the joint motion robot; and a control unit linked with at least one of the treadmill, the user counterweight unit, the joint motion robot, and the joint motion robot support in order to generate a customized control signal according to the user and to transmit the signal. | 12-25-2014 |
20150294049 | BRAKE HILS SYSTEM FOR A RAILWAY VEHICLE - Disclosed is a brake HILS system for a railway vehicle, comprising: a user terminal that receives values relating to braking conditions of a railway vehicle through a user interface and monitors simulation results; a pneumatic brake that includes an electronic control unit, a brake operation unit, a wheelset, a brake caliper, and a wheel slide protection valve and produces pneumatic pressure and transmits a braking force to the wheelset in accordance with the braking conditions from the user terminal; a load cell that is disposed on a wheel or a disc and measures a braking force from the pneumatic pressure; and a modeling unit that simulates the running and braking dynamic characteristics of a railway vehicle in real-time using mathematical models. | 10-15-2015 |
Patent application number | Description | Published |
20090256177 | Semiconductor device including an ohmic layer - In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance. | 10-15-2009 |
20120255616 | METAL-OXIDE/CARBON-NANOTUBE COMPOSITE MEMBRANE TO BE USED AS A P-TYPE CONDUCTIVE MEMBRANE FOR AN ORGANIC SOLAR CELL, METHOD FOR PREPARING SAME, AND ORGANIC SOLAR CELL HAVING IMPROVED PHOTOVOLTAIC CONVERSION EFFICIENCY USING SAME - The present invention relates to a metal-oxide/carbon-nanotube composite membrane to be used as a P-type conductive membrane for an organic solar cell, to a method for preparing same, and to an organic solar cell having improved photovoltaic conversion efficiency using the same. More particularly, the present invention relates to a metal-oxide/carbon-nanotube composite membrane to be used as a P-type conductive membrane for an organic solar cell, wherein said composite membrane is prepared by dispersing single-walled carbon nanotubes in an organic solvent, adding metal oxides to the mixed solution, dispersing the mixed solution to obtain a composite solution, and depositing the thus-obtained composite solution onto a substrate. The method also relates to a method for preparing a metal-oxide/carbon-nanotube composite membrane to be used as a P-type conductive membrane of an organic solar cell, comprising: a step (step 1) of dispersing single-walled carbon nanotubes in an organic solvent; a step (step 2) of adding metal oxides to the mixed solution prepared in step 1, and dispersing the mixed solution to obtain a composite solution; and a step (step 3) of depositing the thus-obtained composite solution onto a substrate. The present invention also relates to an organic solar cell formed by laminating components in the following order: a substrate, an electrode, a photoactive layer, a P-type conductive membrane, and an electrode. The P-type conductive membrane is a metal-oxide/carbon-nanotube composite membrane which is prepared by dispersing single-walled carbon nanotubes in an organic solvent, adding metal oxides to the mixed solution, dispersing the mixed solution to obtain a composite solution, and depositing the thus-obtained composite solution onto a substrate. | 10-11-2012 |
20130029041 | METHOD OF COATING SURFACE OF INORGANIC POWDER PARTICLES WITH SILICON-CARBON COMPOSITE AND INORGANIC POWDER PARTICLES COATED BY THE SAME - The present invention relates to a method of coating the surface of inorganic powder particles with a silicon-carbon composite and to inorganic powder particles coated by the method. More specifically, the invention relates to a method of coating the surface of inorganic powder particles with a silicon-carbon composite by mixing inorganic powder particles with a solid organic silicon polymer and heating the mixture, and to inorganic powder particles coated by the method. | 01-31-2013 |
20130061931 | EFFICIENT ORGANIC SOLAR CELL USING CORE/SHELL METAL OXIDE NANOPARTICLES, AND METHOD FOR MANUFACTURING SAME - The present invention relates to a photoactive layer solution for an efficient organic solar cell including core/shell metal oxide nano-particles, to a method for manufacturing same, and to an organic solar cell including the photoactive layer solution and to a method for manufacturing same. Uniform coating of a substrate having a large area is difficult using the existing PEDOT:PSS. However, using the photoactive layer solution according to the present invention enables P-type metal oxide nano-particles to be directly dispersed on the photoactive layer, thereby having efficiency similar to the existing layer-by-layer (LbL)-type organic solar cell, and enabling a reduction in costs, since there is no need to deposit a separate p buffer layer such as PEDOT:PSS, and the organic solar cell to be manufactured by means of just a simple wet process. Also, application products can be selected through various types of coating methods. | 03-14-2013 |
Patent application number | Description | Published |
20100250675 | SYSTEM AND METHOD FOR TRANSMITTING PERSONAL NETWORKING-BASED BLOG POST, AND SERVER APPLIED TO THE SAME - Disclosed are a system and method for distributing a blog post based on personal networking, and a server to be applied thereto. The system includes a writer terminal unit, which makes a series of settings for forming a blog post containing contents posted by a writer through the writer's blog registered with an online community service, and then distributes the blog post to at least one or more acquaintances blogs registered to personal networking with the writer, sharer/distributor terminal units, which make setting for posting the blog post on the acquaintances blogs, or distributing the blog post to at least one or more other acquaintances blogs registered to personal networking with sharers/distributors, and a service management server, which differentially provides management authority for the blog post to each of the writer and the sharers/distributors, and integrally manages the blog post distributed to a plurality of blogs, based on a path along which the blog post is distributed. The system and method distributes a blog post containing a writer's specific purpose of posting, such as a help-wanted notice, step by step through blogs registered with an online community service, based on trust relationships, thereby providing a notice platform, which is so efficient that an advertiser who writes a blog post, such as a help-wanted notice, can quickly find a qualified person, based on his/her trust relationships. | 09-30-2010 |