Patent application number | Description | Published |
20100255278 | FOAMBOARD SUBSTRATE FOR USE WITH DIGITAL IMAGING SYSTEMS - A printing substrate is provided, wherein the printing substrate includes a top layer; a middle layer, wherein the middle layer is attached to the top layer, and wherein the middle layer further includes a material that is different the material of the top layer; and a bottom layer, wherein the bottom layer is attached to the middle layer, and wherein the middle layer further includes a material that is different than the material of the middle layer and a material that is the same as the material of the top layer; and wherein the printing substrate is adapted specifically for use with use with digital imaging systems such as large, flatbed digital printers and the like. | 10-07-2010 |
20120156402 | PRINTING SUBSTRATE WITH INTEGRATED FRAME - A substrate suitable for use with digital imaging systems such as large-scale digital flatbed printers is provided. This substrate includes a first layer that further includes a durable material suitable for receiving a printed image; a second layer that is attached to the first layer, wherein the second layer further includes a material that is different than the material of the first layer, and wherein the second layer is operative to provide structural support to the first layer. The first layer may include a variety of papers, canvas or canvas-like material, or unbleached, uncoated, high-strength paperboard. The second layer may include a substantially rigid polystyrene core or other rigid or semi-rigid material. A third layer may be attached to the second layer and may include some or all of the components of the first layer. This printing substrate may include an integrated frame for providing structural support to the substrate. | 06-21-2012 |
20140314971 | PRINTING SUBSTRATE WITH INTEGRATED FRAME - A printing substrate for use with digital imaging systems that includes a first layer that further includes a material suitable for receiving a printed image; a second layer attached to the first layer, wherein the second layer further includes a material that is different from and of greater rigidity than the material of the first layer, and wherein the second layer is operative to provide structural support to the first layer; and a frame made from and integral with the printing substrate, wherein the frame surrounds a centrally-placed square or rectangular region of the printing substrate, and wherein the frame further includes multiple foldable regions that are folded over, inward, and downward onto the second layer and secured thereto. | 10-23-2014 |
20150030788 | PRINTING SUBSTRATE WITH INTEGRATED FRAME - A substrate suitable for use with digital imaging systems such as large-scale digital flatbed printers is provided. This substrate includes a first layer that further includes a durable material suitable for receiving a printed image; a second layer that is attached to the first layer, wherein the second layer further includes a material that is different than the material of the first layer, and wherein the second layer is operative to provide structural support to the first layer. The first layer may include a variety of papers, canvas or canvas-like material, or unbleached, uncoated, high-strength paperboard. The second layer may include a substantially rigid polystyrene core or other rigid or semi-rigid material. A third layer may be attached to the second layer and may include some or all of the components of the first layer. This printing substrate may include an integrated frame for providing structural support to the substrate. | 01-29-2015 |
Patent application number | Description | Published |
20090309129 | Semiconductor ESD Device and Method of Making Same - A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included. | 12-17-2009 |
20100321843 | Semiconductor ESD Device and Method of Making Same - A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included. | 12-23-2010 |
20110063763 | Electrostatic Discharge Protection Circuit, Integrated Circuit And Method Of Protecting Circuitry From An Electrostatic Discharge Voltage - Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node. | 03-17-2011 |
20120099229 | Semiconductor ESD Device and Method - An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier. | 04-26-2012 |
20120176710 | Semiconductor ESD Circuit and Method - In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node. | 07-12-2012 |
20120218671 | Semiconductor ESD Device and Method of Making Same - A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included. | 08-30-2012 |
20130019222 | System and Method for Detecting Parasitic Thyristors in an Integrated CircuitAANM Domanski; KrzysztofAACI MuenchenAACO DEAAGP Domanski; Krzysztof Muenchen DEAANM Schneider; JensAACI MuenchenAACO DEAAGP Schneider; Jens Muenchen DEAANM Jungmann; AngelikaAACI UnterhachingAACO DEAAGP Jungmann; Angelika Unterhaching DE - In an embodiment, a method includes retrieving a layout of an integrated circuit design from a non-transitory computer readable medium, identifying a silicon controlled rectifier (SCR) structure in the layout, identifying a current injection site in the layout, and determining if a distance between the identified current injection site and the identified SCR structure is less than a first threshold. A violation is flagged if the determined distance is less than the first threshold. | 01-17-2013 |
20130277712 | Semiconductor ESD Device and Method of Making Same - A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included. | 10-24-2013 |
20140084380 | System and Method for an Integrated Circuit Having Transistor Segments - In accordance with an embodiment, an integrated circuit has a first transistor made of a plurality of first transistor segments disposed in a well area, and a second transistor made of at least one second transistor segment. Drain regions of the plurality of first transistor segments and the at least one second transistor segment are coupled to a common output node. The at least one second transistor segment is disposed in the well area such that an electrostatic discharge pulse applied to a common output node homogenously triggers parasitic bipolar devices coupled to each drain region of the plurality of first transistor segments and the drain region of the at least one second transistor segment. | 03-27-2014 |
20140159207 | ESD Protection Structure, Integrated Circuit and Semiconductor Device - Implementations are presented herein that include an ESD protection structure. The structure may include a plurality of first doped regions forming first terminals of a plurality of transistors, a plurality of second doped regions forming second terminals of the plurality of transistors, and a third doped region surrounding the plurality of first doped regions and the plurality of second doped regions to form a common third terminal of the plurality of transistors. The plurality of first doped regions and the plurality of second doped regions may be arranged in an alternating pattern such that an ESD discharge current received on any one of the plurality of first doped regions dissipates through at least two of the plurality of second doped regions. | 06-12-2014 |
20150144996 | Semiconductor ESD Device and Method of Making Same - A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included. | 05-28-2015 |
20150229126 | Semiconductor ESD Circuit and Method - In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node. | 08-13-2015 |
Patent application number | Description | Published |
20130128968 | Method for predicting a shape of an encoded area using a depth map - A method for predicting a shape of an encoded area using a depth map. The method includes synthesizing a virtual depth map and identifying disoccluded regions in the virtual depth map, wherein the disoccluded regions provide a predicted a shape of an area under compression. | 05-23-2013 |
20130129235 | Image Coding Method - An image coding method. The method includes encoding a first image, the first image having a reduced spatial resolution relative to an input image, wherein values of the first image depend on energy of corresponding areas of the input image, and encoding a first shape information of the shape of a spatial spectrum of the input image. The method further includes reconstructing a second image from the encoded first image, reconstructing a second shape information from the encoded first shape information, and generating a noise image having an intensity described by the second image and having a spectrum shape described by the second shape information. | 05-23-2013 |
20130129244 | Method for coding of stereoscopic depth - A method for coding a stereoscopic depth. The method includes encoding a signal varied in a non-linear relation to the stereoscopic depth so as to obtain a transformed signal, and decoding the transformed signal using an inverse non-linear transformation so as to reconstruct the stereoscopic depth. The dynamics of the transformed signal for small values of the stereoscopic depth are greater than the dynamics of the transformed signal for large values of the stereoscopic depth. | 05-23-2013 |
20140044181 | METHOD AND A SYSTEM FOR VIDEO SIGNAL ENCODING AND DECODING WITH MOTION ESTIMATION - A computer-implemented method for video signal encoding with motion estimation, the video signal comprising frames divided into prediction units, the method comprising the steps of: determining ( | 02-13-2014 |