Patent application number | Description | Published |
20100131744 | METHOD AND SYSTEM OF A PROCESSOR-AGNOSTIC ENCODED DEBUG-ARCHITECTURE IN A PIPELINED ENVIRONMENT - A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system. | 05-27-2010 |
20120011404 | METHOD AND SYSTEM OF A PROCESSOR-AGNOSTIC ENCODED DEBUG-ARCHITECTURE IN A PIPELINED ENVIRONMENT - A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system. | 01-12-2012 |
20120216080 | EMBEDDING STALL AND EVENT TRACE PROFILING DATA IN THE TIMING STREAM - EXTENDED TIMING TRACE CIRCUITS, PROCESSES, AND SYSTEMS - An electronic tracing process includes packing both stall ( | 08-23-2012 |
20150149833 | EMBEDDING STALL AND EVENT TRACE PROFILING DATA IN THE TIMING STREAM - EXTENDED TIMING TRACE CIRCUITS, PROCESSES, AND SYSTEMS - An electronic tracing process includes packing both stall ( | 05-28-2015 |
20150271494 | LOW POWER ULTRA-HD VIDEO HARDWARE ENGINE - A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N. | 09-24-2015 |
20150271512 | DYNAMIC FRAME PADDING IN A VIDEO HARDWARE ENGINE - A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame. | 09-24-2015 |
20150296212 | Processor Instructions for Accelerating Video Coding - A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding. | 10-15-2015 |
20150365696 | OPTICAL FLOW DETERMINATION USING PYRAMIDAL BLOCK MATCHING - An image processing system includes a processor and optical flow determination logic. The optical flow determination logic is to quantify relative motion of a feature present in a first frame of video and a second frame of video with respect to the two frames of video. The optical flow determination logic configures the processor to convert each of the frames of video into a hierarchical image pyramid. The image pyramid comprises a plurality of image levels. Image resolution is reduced at each higher one of the image levels. For each image level and for each pixel in the first frame, the processor is configured to establish an initial estimate of a location of the pixel in the second frame and to apply a plurality of sequential searches, starting from the initial estimate, that establish refined estimates of the location of the pixel in the second frame. | 12-17-2015 |